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? semiconductor components industries, llc, 2011 april, 2011 ? rev. 5 1 publication order number: Q32M210/d Q32M210 precision mixed-signal 32-bit microcontroller introduction Q32M210 is a precision, mixed ? signal 32 ? bit microcontroller. the microcontroller is built on the high performance arm ? cortex ? m3 processor. the microcontroller incorporates a highly configurable sensor interface designed to work directly with a wide range of sensors having multiple characteristics, including specialized electrochemical sensors. the sensor interface includes dual programmable gain amplifiers, dual 16 ? bit analog ? to ? digital converters, triple 10 ? bit digital ? to ? analog converters (for voltage waveform generation and other applications) and three uncommitted, low ? noise opamps with configurable signal multiplexing. flexible connectivity to external non ? volatile memory, personal computers, wireless devices, lcd displays and a wide range of other peripherals is enabled by several digital interfaces including i 2 c, usb (2.0 full ? speed compliant) and a high ? speed spi/sqi interface. the microcontroller features flexible clocking options as well as intelligent failure monitoring of power and application interruptions required by high performance, portable, battery operated applications. all necessary clocks including an internal oscillator, real ? time clock and a dedicated clock for usb operation are available on ? chip (external crystals required for rtc and usb). an embedded power management unit, which incorporates several low power modes, allows application developers to minimize both standby and active power under a wide range of operating conditions. the ultra ? low sleep current makes the microcontroller ideal for applications that remain inactive for long periods of time. a large on ? chip non ? volatile flash memory (256 kb) combined with on ? chip sram (48 kb) supports complex applications and simplifies application development. the flash contains built ? in hardware error checking and correction (ecc) for application reliability. additionally, a configurable dma unit which supports independent peripheral ? to ? memory, memory ? to ? memory, and memory ? to ? peripheral channels provides flexible, low power data transfers without processor intervention. a suite of industry ? standard development tools, hands ? on training and full technical support are available to reduce design cycle time and speed time ? to ? market. ? the Q32M210 microcontroller is pb ? free, halogen free/bfr free and rohs compliant http://onsemi.com tllga ? 140 dual ? row case 513al marking diagram see detailed ordering and shipping information in the package dimensions section on page 50 of this data sheet. ordering information Q32M210 = device code a = assembly site wl = wafer lot yy = year ww = work week g = pb ? free package Q32M210 awlyywwg
Q32M210 http://onsemi.com 2 contents introduction 1 .................................................................................... key features 2 .................................................................................... functional overview 4 ............................................................................. pin definition and descriptions 11 .................................................................... recommended operating conditions 19 ............................................................... esd and latch ? up characteristics 19 .................................................................. electrical characteristics 20 ......................................................................... typical operating characteristics 33 .................................................................. detailed function descriptions 38 .................................................................... example application diagrams 46 .................................................................... key features ultra low ? power and smart power management ? less than 400 a / mhz, up to 16 mhz clock speed ? reliable operation down to 1.8 v; 3.3 v nominal supply voltage ? ultra ? low ? current sleep mode with real ? time clock active (< 750 na) ? low ? current standby mode with register and sram retention (< 26 a) ? integrated power supplies minimize need for external components. only a minimum of external passives is required efficient, powerful and robust processing architecture ? 32 ? bit arm cortex ? m3 cpu ? 256 kb on ? chip flash with integrated hardware ecc for program and user data storage ? 48 kb on ? chip sram ? flexible dma, 4 general ? purpose timers, crc calculator ? no external voltage required for flash write operation low ? noise, low ? leakage, low ? temperature drift, configurable sensor interface ? triple ultra low ? noise opamps with low ? leakage inputs and configurable outputs ? dual on ? chip programmable gain amplifiers (pga) and adcs with flexible input multiplexing and wide dynamic range ? reconfigurable voltage detection unit ? optimal dynamic range scaling of sensor signals ? flexible on ? chip signal routing for dynamic reconfigurability ? minimal temperature drift of gain and offset errors allows for precise calibration ? built ? in temperature sensor predictable operation ? dedicated brown ? out protection circuit prevents execution of code outside of operating range ? integrated hardware ? based ecc for on ? chip flash maintains code and data integrity ? watchdog timer high precision analog ? to ? digital conversion and digital ? to ? analog conversion ? dual 16 ? bit adcs with on ? the ? fly data rate configurability ? triple 10 ? bit dacs with configurable dynamic range precision voltage reference ? on ? chip, low temperature drift (< 50 ppm/ c) voltage reference for adcs and dacs flexible on ? chip clocking ? processor supports speeds up to 16 mhz provided either through internal oscillator or externally supplied clock flexible sensor interconnections ? triple low r on analog multiplexers, including an 8:1 input mux ? quad spst and quad multi ? switches for effective simultaneous connection to different sensors usb 2.0 full ? speed interface ? built ? in transceiver for 2.0 full ? speed compatible (12 mbps) operation with dedicated power supply flexible external interfaes ? configurable interface wakeup pins with configurable pull ? ups and pull ? downs ? 8 configurable gpio interrupts ? dual uarts, dual spi, sqi, i 2 c, pcm (including i2s mode), gpios lcd interface ? up to 112 segments with integrated charge pump and backlight driver (up to 10 ma) packaging ? available in 140 ? pin tllga
Q32M210 http://onsemi.com 3 figure 1. functional overview phy usb controller usbdp usbdn scl sda gpio x 4 if2.[1:0] uart0 gpio x 2 if2 if5 usb jtdi jtdo jtms jtck jrstb memory arbiter peripheral bus system bus instruction bus data system memory rom timer x 4 watchdog timer crc clocks internal rtc oscillator usb oscillator usbxtal1 rtcxtal0 rtcxtal1 ext_clk usbxtal0 vbata vddd vref vddio0 vadc cp0,1 vlcd1 vddio1 pmu regulators rstb vdbl switches spst switches opamps opamp[2:0] multiplexers (8:1, alt0, alt[1:0] a0_in[7:0] pga input multiplexer[1:0] pga[1:0] aux_in[2:0] adc temperature dac[2:0] wakeup controller ecc aaf[1:0] systick flash controller program memory rtc vddusb iref vcp nmi ilv if5.[3:0] vlcd spst1_[a,b] pwm control multi ? switches memory arbiter if0.[3:0] spi0 (sqi) if0 spi1 if1.[3:0] if1 usb memory if3.[1:0] uart1 sqi (io[3:2]) if3 gpio x 32 if4 if4.[31:0] vlcd0 flash nvic arm lcd driver gpio x 2 usrclk x 3 gpio x 4 pcm gpio x 4 clock vss power pord private peripheral bus wakeup x 4 pwm x 4 dma dma control registers adc[1:0] vbat por a2_in, a2_ref, a2_out[a,b] jtag dac[2:0] sensor debug port supervisor oscillator bus controller write i 2 c cortex ? m3 distribution alt1) spst0_[a,b] spst2_[a,b] spst3_[a,b] msw0_[a,b,c] msw1_[a,b,c] msw2_[a,b,c] msw3_[a,b,c] a0_in, a0_ref, a0_out[a,b] a1_in, a1_ref, a1_out[a,b]
Q32M210 http://onsemi.com 4 functional overview operating modes three low ? power operating modes are available 1. run mode ? used during normal program execution; the entire device is fully operational in run mode 2. standby mode ? used for lower current consumption, with paused program execution and fast wakeup 3. sleep mode ? used for ultra low current consumption, with no program execution and restart after wakeup each mode is designed to provide the lowest possible current consumption, while maintaining power to specific parts of the device. run mode run mode provides a low power mode where the entire system is fully functional. in run mode, the device enables the on ? chip vddd digital supply regulator to provide power to the arm cortex ? m3 processor. the processor is clocked from either an internal or an external clock source. the program can be executed from the internal flash or sram. the application can selectively enable or disable sensor interface components, including supply regulators and references, as required. the application may also adjust the device clock frequency through the internal oscillator or through clock divisors to minimize power consumption. the digital and analog interfaces may be configured as required in run mode. internal clock dividers provide all the necessary clocks to the sensor interface and peripherals. while in run mode, the application may switch into either sleep mode or standby mode. standby mode standby mode provides a low power mode where the digital system state is retained. in standby mode, the arm cortex ? m3 processor execution is paused. the vddd digital supply regulator voltage is reduced. the contents of all the registers and sram are retained. the power supervisor automatically disables and powers down the sensor interface components, including the analog supply regulators and references. the application may selectively enable or disable the rtc, rtc alarm, and the wakeup controller. the internal oscillator is automatically disabled. when in standby mode, the device may be switched into run mode by either the rtc alarm or by up to four external events (through the wakeup controller). sleep mode sleep mode provides an ultra ? low power mode where the system is waiting for a wakeup event. in sleep mode, the power supervisor automatically disables and powers down the digital and analog supply regulators, the internal oscillator, and all the sensor interface components. the application may selectively enable or disable the rtc, rtc alarm, and the wakeup controller. when in sleep mode, the device may be switched into run mode by either the rtc alarm or by up to four external events (through the wakeup controller). after exiting sleep mode, the system state is reset and execution starts from the beginning of the rom program. a general purpose retention register is available to store state. the retention register contents are retained after exiting sleep mode. this register may be used by the application to quickly restore its state. power supply the device can powered from a single battery supply such as a 2032 lithium coin cell. the device supplies all required regulated voltages and references on ? chip. this allows the device to operate directly from a single battery supply without the need for external regulators or switches. vbat and vbata the main power supply input for the device is vbat. the supplied voltage to vbat is typically 3.3 v but it can be supplied with any voltage between 1.8 v and 3.6 v. the device will operate reliably across this entire power supply range. this flexibility allows for a wide range of battery types to be directly connected to the device. the sensor interface power supply for the device is vbata. vbata is typically 3.3 v but it can be supplied with any voltage between 1.8 v and 3.6 v. the sensor interface will operate reliably across this entire power supply range however the performance of the sensor interface may be reduced when vbata drops below 2.2 v. vbata also powers the if5 pins. in a typical application, vbata and vbat are both connected directly to the battery supply. to increase the useful operating life of the battery vbata may be externally connected to the on ? chip charge pump output (vdbl) instead of the battery. in this configuration the sensor interface power supply remains nominally 3.5 v even as the battery voltage drops. vbat is monitored by the built ? in power supervisor. vbata is not directly monitored but may be measured through the sensor interface. regulators all required voltages for normal device operation are generated on ? chip. vddd the vddd digital supply regulator (vddd) provides a nominal 1.8 v power supply for the arm cortex ? m3 processor, digital peripheral and memories, including the on ? chip flash. vddd is generated on ? chip and is connected to the digital components internally. it is also available externally. flash memory reads and writes require only a
Q32M210 http://onsemi.com 5 minimum voltage of 1.8 v. no external power management circuitry is required to support flash access. vadc the vadc analog supply regulator (vadc) provides a nominal 1.8 v power supply for the adcs and pgas. this separate supply ensures noise immunity between the analog and digital subsystems. vadc may be enabled or disabled as required to save power. vdbl the vdbl charge pump (vdbl) provides a nominal 3.5 v power supply under any normal operating range battery voltage. vdbl is powered from the dedicated on ? chip charge pump supply regulator (vcp). this separate supply ensures noise immunity between vdbl, the other on ? chip power supplies as well as from the battery. vdbl is normally used to power an lcd segment display and associated backlight or any other external devices requiring a fixed, high voltage rail. vdbl may also be used to power the sensor interface. this is useful when a fixed, higher voltage rail is required for the sensor interface compared to the battery voltage. ilv an on ? chip programmable current sink (ilv) is available to adjust the amount of current from vdbl through an led backlight. in a typical configuration an led is connected between vdbl and ilv. the application controls the led brightness by adjusting the current setting. vref precision voltage reference the device provides an on ? chip low ? temperature drift reference voltage, vref. vref is factory calibrated to 0.9 v. vref is available externally and is also connected internally to the adcs and dacs for their reference voltages. i/o pin supplies the device?s i/o pins are powered from multiple supplies. this allows the device to match its i/o voltage levels to external devices as required. one bank of digital i/o pins is powered from vddio0. the voltage applied to vddio0 determines the logic level for the associated pins. a second bank of mixed signal i/o pins is powered from vddio1. the voltage applied to vddio1 determines the digital logic level for the associated pin. when the mixed signal i/o pins are configured for lcd operation, vddio1 must be at or above vlcd supply voltage for proper operation. the usb pins usbdp and usbdn are powered directly from vddusb. the if5 pins are powered directly from vbata. all analog signal pins are powered directly from vbata. power supervisor, power ? on reset, and brown ? out protection the device contains a dedicated hardware power supervisor for monitoring the supply voltages. the power supervisor ensures the device operates deterministically, and without any unexpected behavior during all supply conditions. the power supervisor releases the internal power ? on reset (por) when the supply voltage on vbat exceeds the minimum threshold for proper operation. the release of por enables the vddd digital supply regulator. the power supervisor continues to monitor vbat. if vbat drops below the minimum threshold for proper operation the device is reset. no external circuitry is required for proper device startup. all required start ? up delays and reset thresholds are generated on ? chip. the rstb pin may be left floating during startup. the arm cortex ? m3 processor and all digital subsystem components including the flash, sram, and peripherals will operate reliability down to a nominal vddd supply voltage of 1.8 v. in run mode, the power supervisor continually monitors vddd. if vddd drops below the minimum threshold for proper operation the device is reset. the power supervisor is automatically disabled in sleep mode and standby mode to save power. supply monitor during run mode, the actual voltage levels for vbat, vbata, vref, and vadc can be measured through either one of the adc channels. this allows the application to determine t he actual supply levels and appropriately handle the graceful shutdown of the system when the battery approaches its useful end ? of ? life. additional voltages may be monitored through one of the auxiliary inputs. in a system configuration where the sensor interface may be supplied from either the battery or the vdbl charge pump, the application can use the measured vbat voltage level to determine whether to enable vdbl or continue to supply the sensor interface from the battery. external reset the device contains an external reset pin (rstb). when rstb is asserted, the digital subsystem including the arm cortex ? m3 processor is reset. the real ? time clock counters are not reset by an external reset. the rstb function is only available in run mode. asserting the rstb pin during the power ? on reset sequence will prevent the arm cortex ? m3 processor from running. the system will be held in reset until the pin is released. rstb can be left floating. system wakeup wakeup occurs when the device is switched from standby mode or sleep mode into run mode. this can be accomplished through one of the wakeup mechanisms. the wakeup controller allows for up to four external events to wake up the system. two if5 pins (if5.0, if5.1) will wakeup the system when a high ? to ? low transition is detected. two if5 pins (if5.2, if5.3) will wakeup the system when a low ? to ? high transition is detected. the rtc alarm can also be configured to wakeup the system at a predetermined time.
Q32M210 http://onsemi.com 6 clocking the device contains several clock generators and clock i/o capability . after power ? on reset, the device selects the internal oscillator as the system clock source. the default clock frequency at por is 3 mhz. after boot, the application may select another frequency or switch to another clock source. the device may select the real ? time crystal oscillator (32.768 khz) as the clock source, when low operating frequencies are required to save power. internal oscillator the device contains a reconfigurable, factory calibrated internal oscillator. the calibration settings are stored in the on ? chip flash. settings are available for all integer frequencies in the normal operating range (1 mhz to 16 mhz). finer calibration is possible. the default setting after power ? on reset is 3 mhz. the application can switch to any operating frequency after entering run mode. external clock the device contains an external clock i/o pin (ext_clk). ext_clk may be used as a clock source for the entire system or as a clock output. the application may switch to use an externally supplied clock or output a clock after boot. if neither function is desired ext_clk may be left floating. an external clock detection circuit is included that will automatically switch the system to the internal oscillator, if the external clock is selected, but no clock signal is detected. when ext_clk is used as an output, the frequency of the output clock can be divided before ext_clk is output. real ? time clock the device contains an ultra low ? power real ? time clock (rtc). the rtc includes a real ? time crystal oscillator, read ? write rtc counters, and a configurable alarm. the real ? time crystal oscillator utilizes a 32.768 khz external crystal. the rtc may be enabled or disabled in each of the three operating modes. the rtc is powered directly from vbat. this allows the rtc to continue to run when the vddd digital supply regulator voltage is reduced in standby mode or disabled in sleep mode and thus the system date and time information are always maintained. the rtc is reset after the initial power ? on reset but remains operational through a digital reset (rstb or watchdog) and operating mode switching. the alarm function can be configured to wake ? up the system from standby mode or sleep mode at a pre ? determined time. the alarm will also generate an interrupt to the arm cortex ? m3 processor. the alarm can be configured for absolute mode or relative mode. in relative mode, the alarm is automatically reloaded after each alarm trigger. this is useful for extremely low ? duty ? cycle applications that require periodic polling. usb crystal oscillator the device contains a dedicated usb crystal oscillator. the oscillator requires an external 48 mhz crystal for compliance with the usb interface specification. the clock output is used internally for the usb phy and usb core. during usb operation the arm cortex ? m3 processor and all other system blocks continue to run on the slower system clock. this allows the device to achieve low system current even while the usb interface is active. the usb crystal oscillator can be enabled or disabled. clock divisors on ? chip clock divisors and prescalers are available to provide selectable frequencies to the arm cortex ? m3 processor, sensor interface, peripherals and external interfaces. these divided clocks are derived from the root clock source and may be configured independently. this adjustability allows the optimum clock frequency to be selected for each system component. sensor interface opamps three uncommitted low ? noise opamps are available. each opamp is directly powered from the vbata supply for achieving high input dynamic range for sensor interface signals. each of the opamp?s positive and negative terminals is brought out to a dedicated input pin on the device. each opamp output terminal is connected to two dedicated output pins. an internal switch selects between output to one or both of the output pins, allowing for dynamic reconfigurability of the external opamp feedback network. signal multiplexing a comprehensive input multiplexing scheme allows for flexible interconnection of a wide range of sensors and external circ uits to be connected to the sensor interface. the input multiplexing consists of: ? an 8:1 analog multiplexer ? connects one of 8 low ? leakage input pins to an opamp negative terminal ? a 3:1 analog multiplexer ? connects one of 3 low ? leakage input pins to an alternate sensor node (alt0) and optionally to an opamp negative terminal ? a 5:1 analog multiplexer ? connects one of 5 low ? leakage input pins to an alternate sensor node (alt1) and optionally to an opamp negative terminal each multiplexer signal path features low ron characteristics providing nearly transparent signal routing for any external sensor. the input multiplexer configuration may be changed on ? the ? fly by the application. dual pga and adc two independent 16 ? bit analog ? to ? digital converters (adcs) are available. the adcs provide a very high resolution, a high degree of linearity, as well as low gain and offset temperature drifts. each adc is coupled with a
Q32M210 http://onsemi.com 7 programmable gain amplifier (pga) allowing signals to be sampled without external buffering. the adc data rate is reconfigurable and a wide range of data rates are possible. each adc conversion takes a fixed time resulting in a deterministic, periodic sampling. lower data rates may be configured to achieve a higher effective dynamic range. the adcs operate rail ? to ? rail from 0 v to v adc (1.8 v) using the internal vref precision voltage reference (0.9 v). unsigned or two?s complement output samples are provided to the arm cortex ? m3 processor and synchronized to the periodic adc interrupt. the dma may also be used to transfer samples directly from the adc to sram. each pga and adc has 16 multiplexed inputs allowing a wide range of sensor interface signals to be measured. in addition, power supply voltages are available as measurement inputs for application level supply monitoring. programmable gain amplifiers a pga is used to directly feed each of the adc inputs. the pgas operate in either single ? ended mode or differential mode. single ? ended operation is obtained by setting one pga input to vss. differential operation is obtained by routing signals to each of the two pga inputs. the resulting voltage is amplified, anti ? alias filtered, and output into the adc. a wide range of gain steps from 0 db to 36 db allow for optimal adjustment of the pga output to match the dynamic range of the adc. pga1 operates in one of three input modes. each input mode provides a different common ? mode voltage range with linearity characteristics and tradeoffs. the application may choose different pga1 operating modes depending on the type of measurement being made. pga0 operates in a single input mode only. automatic voltage detection automatic voltage detection is available on pga0. when enabled, the pga0 will output an interrupt to the arm cortex ? m3 processor when the pga0 output voltage exceeds the configured threshold. to save power the adcs may be disabled while waiting for the detection signal. auxiliary inputs three auxiliary inputs provide a direct connection to the pga and adc multiplexers. external voltages such as thermistor networks may be connected to any of these high impedance inputs for direct measurement with the adc. triple dac three independent 10 ? bit dacs are available. each dac output is individually controlled by the arm cortex ? m3 processor. the dacs provide a high degree of linearity, low gain and offset temperature drift, and are monotonic within the normal operating range. the dynamic range of dac0 is reconfigurable. the 10 ? bit output range may be mapped into one of three ranges: 1 x vref, 2 x vref, or 3 x vref. this reconfigurable dynamic mapping allows a tradeoff between lsb resolution and dynamic range. the dynamic range of dac1 and dac2 is fixed to 2 x vref. temperature sensor the device contains a built ? in temperature sensor. the temperature sensor works by generating a differential voltage that varies linearly with temperature. the voltage is routed into the pga resulting in a single ? ended output voltage measurable by the adc. the temperature sensor is calibrated during factory production by on semiconductor. the calibration value is stored in the flash. the device junction temperature may be determined based on the calibration factor and converted adc output value. spst switches the device contains four analog general ? purpose, low ? leakage, low ? ron, single ? pole single ? throw switches (spsts). each spst consists of 2 ports ? a and b. the spst connection is determined by the application and may be changed in real ? time. port a can be connected or disconnected from port b. the spsts can be used for routing both power supplies and signals. each spst is designed to conduct a continuous current of up to 10 ma. this provides sufficient current bandwidth to supply power to external devices such as lcd displays or wireless transceivers. when routing signals through the spst, the low ? leakage characteristics allow the switch to create a high isolation between a measurement node and the sensor interface. the application may connect the measurement node to the sensor interface through the spst as required. the low ? leakage characteristics allow the spst to be added to the signal chain without interfering with the impedance properties of the measurement node. multi ? switches the device contains four analog general ? purpose, low ? leakage, low ? ron multi ? switches (msws). each msw consists of 3 ports ? port a, port b, and port c (common). the msw connection is determined by the application and may be changed in real ? time. the msw may be configured to connect a to c, b to c, a and b to c, or neither to c. a signal of interest may be connected to the common port, and selectively routed to a, b, or a and b. alternately, two signals of interest may be connected to a and b, respectively, and either one selectively routed to c. the msws may be used for routing both power supplies and signals. each msw is designed to conduct a continuous current of up to 10 ma. this provides sufficient current bandwidth to supply power to external devices such as lcd displays or wireless transceivers. the msws may be configured to switch based on the on ? chip reconfigurable pulse ? width modulator (pwm).
Q32M210 http://onsemi.com 8 the pwm on/off duty cycle time can be configured by the application allowing the msws to act as a power regulator. arm cortex ? m3 processor the arm cortex ? m3 processor is a 32 ? bit risc controller specifically designed to meet the needs of advanced, high ? performance, low ? power applications. the arm cortex ? m3 processor provides outstanding computational performance and exceptional system response to interrupts while providing small core footprint, industry leading code density enabling smaller memories, reduced pin count and low power consumption. the Q32M210 implementation of the arm cortex ? m3 processor contains all necessary peripherals and bus systems to provide a complete device optimized for battery powered sensor interface applications. memories flash memory 256 kb flash is available for storage of application code and data. flash memory can be written one or more words at a time. each page must be erased between writes to a flash word. the flash memory can be erased as a set all at once or in individual 2 kb pages. an additional reserved block of flash memory is used to store factory calibration information provided by on semiconductor. this block can not be written by the application. the arm cortex ? m3 processor executes application code directly from flash with zero wait states. flash error checking and correction a dedicated hardware block performs real ? time error checking and correction of the flash. additional parity bits are stored automatically for each word in the flash. the hardware ecc is able to detect up to 2 ? bit errors per word or detect and correct 1 ? bit error per word. the hardware ecc operates as each word is read from the flash. an interrupt can be generated upon correction of a bit error and a bus fault will be generated when a bit error is detected, but cannot be corrected. sram 48 kb of low ? power sram is available for storage of intermediate data as well as application code. rom an on ? chip rom includes boot functionality as well as firmware routines supporting writing to flash in an application. external interrupt controller eight configurable external interrupt sources may be connected to any eight gpio pins on the device. this is in addition to a dedicated interrupt for the wakeup controller. each interrupt may be individually configured for positive edge triggering, negative edge triggering, high level triggering, or low level triggering. a dedicated non ? maskable interrupt (nmi) pin is connected directly to the arm cortex ? m3 processor. a logic high level on this pin will trigger the interrupt handler for the nmi. dma a flexible dma unit supports low overhead data exchange between system blocks. memory ? to ? peripheral, peripheral ? to ? memory, and memory ? to ? memory modes are available. four simultaneous dma channels can be established with configurable sources and sinks. the dma can be used with the uart, spi, sqi, i 2 c, usb, and pcm interfaces, as well as the adcs and dacs. the dma operates in the background allowing the arm cortex ? m3 processor to execute other applications or to reduce its operating frequency to conserve power. general ? purpose timers the device contains four general ? purpose timers. each timer features a 12 ? bit countdown mode, an external interrupt to the arm cortex ? m3 processor, a dedicated prescaler, and the ability to poll the counter value. these four general ? purpose timers are in addition to the 24 ? bit systick timer included as part of the arm cortex ? m3 processor. crc engine a 16 ? bit hardware crc engine is available. the crc engine may be used to ensure data integrity of application code and data. the crc engine?s input port and output port are directly accessible from the arm cortex ? m3 processor. the starting vector may be set to any value. subsequently, data words of multiple bit lengths can be added to the crc. the 16 ? bit crc ? ccitt polynomial is used. watchdog timer the device contains a digital watchdog timer. the watchdog timer is intended to prevent an indefinite system hang when an application error occurs. the application must periodically refresh the watchdog counter during operation. if a watchdog timeout occurs an initial alert interrupt is generated. if a subsequent watchdog timeout occurs, a system reset is generated. the initial alert may be used to gracefully shut down the system. dual uart two general ? purpose uart interfaces are available. the uarts support the standard rs232 protocol and baud rates at the vddio0 voltage level. the uart format is fixed at one start bit, eight data bits, and one stop bit. the baud rate is configurable over a wide range of baud rates up to 250 kbaud using a 1 mhz source clock. the uart interfaces may be used either directly from the arm cortex ? m3 processor or through the dma controller.
Q32M210 http://onsemi.com 9 dual spi two spi interfaces are available supporting both master and slave operation. each synchronous 4 ? wire interface provides a clock, chip select, serial data in, and serial data out connection. the spi interface can be used to interface with external devices such as non ? volatile memories, displays, and wireless transceivers. the spi interfaces can be used either directly from the arm cortex ? m3 processor or through the dma controller sqi the primary spi interface can be configured to operate in sqi (serial quad interface) mode. in sqi mode 4 bits are interchanged simultaneously instead of 1 bit in spi mode. in this way, the throughput of the interface is increased by a factor of 4 for the same clock frequency. the sqi interface is typically used to access large, external nvm arrays. i 2 c the i 2 c interface supports both master and slave operation. the interface operates at normal speed (100 kbit/sec) and high speed (400 kbit/sec). on ? chip pull ? up resistors are available on the sda and scl pins. the i 2 c interface can be used either directly from the arm cortex ? m3 processor or through the dma controller. the i 2 c slave address is programmable by the application. pcm the pulse ? code modulation (pcm) interface provides a data connection between the device and external devices such as bluetooth or audio processors. the pcm interface can operate both in master and slave mode. the master device of a pcm transfer generates the frame signal. the pcm interface can be used either directly from the arm cortex ? m3 processor or through the dma controller. two dma channels are used with the pcm interface ? one for rx, and one for tx. the pcm interface supports a wide variety of interface protocols by reconfiguring the frame type and width, word size and clock polarities. the pcm interface supports the i2s data format directly for connecting to an i2s compatible audio device. audio data can be streamed to and from the audio device over the pcm interface in i2s mode. gpio gpio pins can be configured as input or output signals. the pins are powered from vddio0, vddio1, or vbata providing flexibility in the i/o voltage levels available. different i/o voltage levels may be supplied to vddio0 and vddio1 within the normal operating range. gpio functionality is shared with alternate functions on most gpio pins. the gpio or alternate function is selected through the application. usb the usb interface provides connectivity between the arm cortex ? m3 processor and a usb host. the usb interface operates as a usb full speed device (12 mbit/sec). the usb physical interface (phy) is powered directly from vddusb. a minimum supply of 3 v is required. typically vddusb will be powered from the +5 v provided by the usb bus regulated down to 3.3 v. the interface requires a 48 mhz clock which is provided through the usb crystal oscillator. an external 48 mhz crystal is required for this interface to operate. the usb interface operates on a separate clock domain allowing the rest of the system to continue to run on the slower internal oscillator or external clock source. this enables reduced power consumption, since the arm cortex ? m3 processor can operate at a lower frequency than the usb clock when usb is operational. the usb interface interfaces to the arm cortex ? m3 processor through memory ? mapped control registers and interrupts. the dma may be used to transfer data between the usb interface and the sram directly. lcd the device provides an on ? chip lcd driver capable of driving up to 112 display segments of a 1/3 bias, 1/4 duty cycle lcd display. the interface consists of four common (com) lines and twenty ? eight (28) segment (seg) lines. the drive voltages are sourced from vlcd and consist of four voltages (0 v, 1/3 x vlcd, 2/3 x vlcd, and vlcd). lcd backlight the lcd backlight driver provides an application controlled current sink. it is programmable to sink nominally between 0 ma to 10 ma. an lcd backlight may be connected between vdbl and ilv. the current passing through the led is regulated based on the current setting set by the application. jtag the device contains a dedicated jtag port for interfacing to the arm cortex ? m3 processor and memories. the device implements the standard jtag ? dp protocol provided by arm, providing compatibility with many external debugging systems.
Q32M210 http://onsemi.com 10 figure 2. pin definition and descriptions
Q32M210 http://onsemi.com 11 table 1. pin definitions pin pin name (note 6) type (note 1) direction (note 2) pull ? up / pull ? down (note 3) pin power supply function 140 tllga primary (note 4) alternate 1 alternate 2 alternate 3 b4 usbdp d i/o ? vddusb usbdp ? ? ? a5 usbdn d i/o ? vddusb usbdn ? ? ? b44 scl d i/o pu vddio0 scl ? ? ? a51 sda d i/o pu vddio0 sda ? ? ? a48 if0.0 d i/o pu vddio0 spi0_clk gpio32 ? ? a53 if0.1 d i/o pu vddio0 spi0_cs gpio33 usrclk0 ? a57 if0.2 d i/o pu vddio0 spi0_si gpio34 usrclk1 sqi_sio[1] a56 if0.3 d i/o pu vddio0 spi0_so gpio35 usrclk2 sqi_sio[0] a47 if1.0 d i/o pu vddio0 spi1_clk gpio36 pcm_clk ? b39 if1.1 d i/o pu vddio0 spi1_cs gpio37 pcm_fr ? a52 if1.2 d i/o pu vddio0 spi1_si gpio38 pcm_si ? b45 if1.3 d i/o pu vddio0 spi1_so gpio39 pcm_so ? b48 if2.0 d i/o pu vddio0 uart0_tx gpio40 ? ? a49 if2.1 d i/o pu vddio0 uart0_rx gpio41 ? ? b41 if3.0 d i/o pu vddio0 uart1_tx gpio42 sqi_sio[2] ? a54 if3.1 d i/o pu vddio0 uart1_rx gpio43 sqi_sio[3] ? a2 if4.0 m i/o pd vddio1 gpio0 com0 ? ? a1 if4.1 m i/o pd vddio1 gpio1 com1 ? ? b1 if4.2 m i/o pd vddio1 gpio2 com2 ? ? a76 if4.3 m i/o pd vddio1 gpio3 com3 ? ? b64 if4.4 m i/o pd vddio1 gpio4 seg0 ? ? a75 if4.5 m i/o pd vddio1 gpio5 seg1 ? ? b63 if4.6 m i/o pd vddio1 gpio6 seg2 ? ? a74 if4.7 m i/o pd vddio1 gpio7 seg3 ? ? a72 if4.8 m i/o pd vddio1 gpio8 seg4 ? ? b61 if4.9 m i/o pd vddio1 gpio9 seg5 ? ? b60 if4.10 m i/o pd vddio1 gpio10 seg6 ? ? a70 if4.11 m i/o pd vddio1 gpio11 seg7 ? ? b59 if4.12 m i/o pd vddio1 gpio12 seg8 ? ? a69 if4.13 m i/o pd vddio1 gpio13 seg9 ? ? b58 if4.14 m i/o pd vddio1 gpio14 seg10 ? ? a68 if4.15 m i/o pd vddio1 gpio15 seg11 ? ? b57 if4.16 m i/o pd vddio1 gpio16 seg12 ? ? a67 if4.17 m i/o pd vddio1 gpio17 seg13 ? ? b56 if4.18 m i/o pd vddio1 gpio18 seg14 ? ? a66 if4.19 m i/o pd vddio1 gpio19 seg15 ? ? b55 if4.20 m i/o pd vddio1 gpio20 seg16 ? ? a65 if4.21 m i/o pd vddio1 gpio21 seg17 ? ? 1. types: d ? digital, m ? mixed signal, a ? analog, s ? supply 2. direction: i ? input, o ? output, i/o ? input or output 3. pu ? pull ? up, pd ? pull ? down. most pull ? up and pull ? downs may be disconnected in firmware 4. primary function is the power ? on default. alternate functions may be selected in firmware 5. test must be connected to vss for proper device operation 6. all pins with the same name must be shorted together for proper device operation 7. if5.0 can be used as an analog external input to programmable gain amplifiers
Q32M210 http://onsemi.com 12 table 1. pin definitions pin function pin power supply pull ? up / pull ? down (note 3) direction (note 2) type (note 1) pin name (note 6) 140 tllga alternate 3 alternate 2 alternate 1 primary (note 4) pin power supply pull ? up / pull ? down (note 3) direction (note 2) type (note 1) pin name (note 6) a64 if4.22 m i/o pd vddio1 gpio22 seg18 ? ? a63 if4.23 m i/o pd vddio1 gpio23 seg19 ? ? b53 if4.24 m i/o pd vddio1 gpio24 seg20 pwm0 ? a62 if4.25 m i/o pd vddio1 gpio25 seg21 pwm1 ? b52 if4.26 m i/o pd vddio1 gpio26 seg22 pwm2 ? a61 if4.27 m i/o pd vddio1 gpio27 seg23 pwm3 ? b51 if4.28 m i/o pd vddio1 gpio28 seg24 ? ? a60 if4.29 m i/o pd vddio1 gpio29 seg25 ? ? b50 if4.30 m i/o pd vddio1 gpio30 seg26 ? ? a59 if4.31 m i/o pd vddio1 gpio31 seg27 ? ? b47 nmi d i pd vddio0 nmi ? ? ? a12 if5.0 (note 7) m i/o pu vbata wakeup0 gpio44 ? ? b10 if5.1 d i/o pu vbata gpio45 wakeup1 ? ? a11 if5.2 d i/o pd vbata gpio46 wakeup2 ? ? b9 if5.3 d i/o pd vbata gpio47 wakeup3 ? ? b42 rstb d i pu vddio0 rstb ? ? ? b38 jtdi d i pd vddio0 jtdi ? ? ? b40 jtdo d o ? vddio0 jtdo ? ? ? a46 jtms d i pu vddio0 jtms ? ? ? a55 jtck d i vddio0 jtck ? ? ? a45 jrstb d i pu vddio0 jrstb ? ? ? a20 dac0 a o ? vbata dac0 ? ? ? a21 dac1 a o ? vbata dac1 ? ? ? b18 dac2 a o ? vbata dac2 ? ? ? a29 aux_in0 a i ? vbata aux_in0 ? ? ? b24 aux_in1 a i ? vbata aux_in1 ? ? ? a23 aux_in2 a i ? vbata aux_in2 ? ? ? a37 aaf0 a i/o ? vbata aaf0 ? ? ? b32 aaf1 a i/o ? vbata aaf1 ? ? ? b17 msw0_a a i/o ? vbata msw0_a ? ? ? b16 msw0_b a i/o ? vbata msw0_b ? ? ? a19 msw0_c a i/o ? vbata msw0_c ? ? ? a18 msw1_a a i/o ? vbata msw1_a ? ? ? a17 msw1_b a i/o ? vbata msw1_b ? ? ? b15 msw1_c a i/o ? vbata msw1_c ? ? ? b14 msw2_a a i/o ? vbata msw2_a ? ? ? b13 msw2_b a i/o ? vbata msw2_b ? ? ? 1. types: d ? digital, m ? mixed signal, a ? analog, s ? supply 2. direction: i ? input, o ? output, i/o ? input or output 3. pu ? pull ? up, pd ? pull ? down. most pull ? up and pull ? downs may be disconnected in firmware 4. primary function is the power ? on default. alternate functions may be selected in firmware 5. test must be connected to vss for proper device operation 6. all pins with the same name must be shorted together for proper device operation 7. if5.0 can be used as an analog external input to programmable gain amplifiers
Q32M210 http://onsemi.com 13 table 1. pin definitions pin function pin power supply pull ? up / pull ? down (note 3) direction (note 2) type (note 1) pin name (note 6) 140 tllga alternate 3 alternate 2 alternate 1 primary (note 4) pin power supply pull ? up / pull ? down (note 3) direction (note 2) type (note 1) pin name (note 6) a16 msw2_c a i/o ? vbata msw2_c ? ? ? a15 msw3_a a i/o ? vbata msw3_a ? ? ? b12 msw3_b a i/o ? vbata msw3_b ? ? ? a14 msw3_c a i/o ? vbata msw3_c ? ? ? a58 nc ? ? ? ? nc ? ? ? a8 vdbl s o ? ? vdbl ? ? ? a10 vbata s i ? ? vbata ? ? ? b20 vbata s i ? ? vbata ? ? ? a73 vbata s i ? ? vbat ? ? ? b62 vddd s o ? ? vddd ? ? ? a7 ilv a i/o ? vlcd ilv ? ? ? a44 vddio0 s i ? ? vddio0 ? ? ? b37 vddio0 s i ? ? vddio0 ? ? ? a50 vddio0 s i ? ? vddio0 ? ? ? b43 vddio0 s i ? ? vddio0 ? ? ? b3 vddio1 s i ? ? vddio1 ? ? ? b49 vddio1 s i ? ? vddio1 ? ? ? b54 vddio1 s i ? ? vddio1 ? ? ? a71 vddio1 s i ? ? vddio1 ? ? ? a4 vddusb s i ? ? vddusb ? ? ? a38 vref s o ? ? vref ? ? ? a13 iref s o ? ? iref ? ? ? a39 vadc s o ? ? vadc ? ? ? b6 vlcd0 a o ? vlcd vlcd0 ? ? ? a6 vlcd1 a o ? vlcd vlcd1 ? ? ? b5 vlcd s i ? ? vlcd ? ? ? b8 cp0 a o ? vlcd cp0 ? ? ? b7 cp1 a o ? vlcd cp1 ? ? ? a9 vcp s o ? ? vcp ? ? ? b2 usbxtal0 a i/o ? vddio1 usbxtal0 ? ? ? a3 usbxtal1 a i/o ? vddio1 usbxtal1 ? ? ? b19 rtcxtal0 a i/o ? vbat rtcxtal0 ? ? ? a22 rtcxtal1 a i/o ? vbat rtcxtal1 ? ? ? b46 extclk d i/o ? vddio0 extclk ? ? ? b25 alt0 a i/o ? vbata alt0 ? ? ? a30 alt1 a i/o ? vbata alt1 ? ? ? a31 a0_in0 a i/o ? vbata a0_in0 ? ? ? b26 a0_in1 a i/o ? vbata a0_in1 ? ? ? 1. types: d ? digital, m ? mixed signal, a ? analog, s ? supply 2. direction: i ? input, o ? output, i/o ? input or output 3. pu ? pull ? up, pd ? pull ? down. most pull ? up and pull ? downs may be disconnected in firmware 4. primary function is the power ? on default. alternate functions may be selected in firmware 5. test must be connected to vss for proper device operation 6. all pins with the same name must be shorted together for proper device operation 7. if5.0 can be used as an analog external input to programmable gain amplifiers
Q32M210 http://onsemi.com 14 table 1. pin definitions pin function pin power supply pull ? up / pull ? down (note 3) direction (note 2) type (note 1) pin name (note 6) 140 tllga alternate 3 alternate 2 alternate 1 primary (note 4) pin power supply pull ? up / pull ? down (note 3) direction (note 2) type (note 1) pin name (note 6) a32 a0_in2 a i/o ? vbata a0_in2 ? ? ? b27 a0_in3 a i/o ? vbata a0_in3 ? ? ? a33 a0_in4 a i/o ? vbata a0_in4 ? ? ? b28 a0_in5 a i/o ? vbata a0_in5 ? ? ? a34 a0_in6 a i/o ? vbata a0_in6 ? ? ? b29 a0_in7 a i/o ? vbata a0_in7 ? ? ? a35 a0_in a i ? vbata a0_in ? ? ? a28 a1_in a i ? vbata a1_in ? ? ? a26 a2_in a i ? vbata a2_in ? ? ? b30 a0_ref a i ? vbata a0_ref ? ? ? b22 a1_ref a i ? vbata a1_ref ? ? ? a24 a2_ref a i ? vbata a2_ref ? ? ? b31 a0_outa a o ? vbata a0_outa ? ? ? a36 a0_outb a o ? vbata a0_outb ? ? ? b23 a1_outa a o ? vbata a1_outa ? ? ? a27 a1_outb a o ? vbata a1_outb ? ? ? b21 a2_outa a o ? vbata a2_outa ? ? ? a25 a2_outb a o ? vbata a2_outb ? ? ? a43 spst0_a a i/o ? vbata spst0_a ? ? ? b36 spst0_b a i/o ? vbata spst0_b ? ? ? a42 spst1_a a i/o ? vbata spst1_a ? ? ? b35 spst1_b a i/o ? vbata spst1_b ? ? ? a41 spst2_a a i/o ? vbata spst2_a ? ? ? b34 spst2_b a i/o ? vbata spst2_b ? ? ? a40 spst3_a a i/o ? vbata spst3_a ? ? ? b33 spst3_b a i/o ? vbata spst3_b ? ? ? b11 test (note 5) a i ? ? test (connect to vss) ? ? ? thermal vss s ? ? ? vss ? ? ? 1. types: d ? digital, m ? mixed signal, a ? analog, s ? supply 2. direction: i ? input, o ? output, i/o ? input or output 3. pu ? pull ? up, pd ? pull ? down. most pull ? up and pull ? downs may be disconnected in firmware 4. primary function is the power ? on default. alternate functions may be selected in firmware 5. test must be connected to vss for proper device operation 6. all pins with the same name must be shorted together for proper device operation 7. if5.0 can be used as an analog external input to programmable gain amplifiers
Q32M210 http://onsemi.com 15 table 2. detailed pin descriptions pin name description usbdp usb interface positive terminal usbdn usb interface negative terminal scl i 2 c interface clock sda i 2 c interface data if0.0 primary spi interface clock / general purpose i/o if0.1 primary spi interface chip select / general purpose i/o / user clock output if0.2 primary spi interface data input / general purpose i/o / user clock output / sqi serial i/o 1 if0.3 primary spi interface data output / general purpose i/o / user clock output / sqi serial i/o 0 if1.0 secondary spi interface clock line / general purpose i/o / pcm interface clock if1.1 secondary spi interface chip select / general purpose i/o / pcm interface frame if1.2 secondary spi interface data input / general purpose i/o / pcm interface data input if1.3 secondary spi interface data output / general purpose i/o / pcm interface data output if2.0 primary uart transmit line / general purpose i/o if2.1 primary uart receive line / general purpose i/o if3.0 secondary uart transmit line / general purpose i/o / sqi serial i/o 2 if3.1 secondary uart receive line / general purpose i/o / sqi serial i/o 3 if4.0 lcd backplane drive output (com0) / general purpose i/o if4.1 lcd backplane drive output (com1) / general purpose i/o if4.2 lcd backplane drive output (com2) / general purpose i/o if4.3 lcd backplane drive output (com3) / general purpose i/o if4.4 lcd segment output / general purpose i/o if4.5 lcd segment output / general purpose i/o if4.6 lcd segment output / general purpose i/o if4.7 lcd segment output / general purpose i/o if4.8 lcd segment output / general purpose i/o if4.9 lcd segment output / general purpose i/o if4.10 lcd segment output / general purpose i/o if4.11 lcd segment output / general purpose i/o if4.12 lcd segment output / general purpose i/o if4.13 lcd segment output / general purpose i/o if4.14 lcd segment output / general purpose i/o if4.15 lcd segment output / general purpose i/o if4.16 lcd segment output / general purpose i/o if4.17 lcd segment output / general purpose i/o if4.18 lcd segment output / general purpose i/o if4.19 lcd segment output / general purpose i/o if4.20 lcd segment output / general purpose i/o if4.21 lcd segment output / general purpose i/o if4.22 lcd segment output / general purpose i/o if4.23 lcd segment output / general purpose i/o if4.24 lcd segment output / general purpose i/o / pulse ? width modulator 0 output if4.25 lcd segment output / general purpose i/o / pulse ? width modulator 1 output if4.26 lcd segment output / general purpose i/o / pulse ? width modulator 2 output if4.27 lcd segment output / general purpose i/o / pulse ? width modulator 3 output
Q32M210 http://onsemi.com 16 table 2. detailed pin descriptions pin name description if4.28 lcd segment output / general purpose i/o if4.29 lcd segment output / general purpose i/o if4.30 lcd segment output / general purpose i/o if4.31 lcd segment output / general purpose i/o nmi non ? maskable interrupt if5.0 wakeup input 0, falling edge / general purpose i/o / external signal to programmable gain amplifiers if5.1 wakeup input 1, falling edge / general purpose i/o if5.2 wakeup input 2, rising edge / general purpose i/o if5.3 wakeup input 3 rising edge / general purpose i/o rstb reset input jtdi jtag data input jtdo jtag data output jtms jtag mode select jtck jtag clock jrstb jtag reset dac0 digital ? to ? analog converter 0 output dac1 digital ? to ? analog converter 1 output dac2 digital ? to ? analog converter 2 output aux_in0 auxiliary input 0 ? external signal input to programmable gain amplifiers aux_in1 auxiliary input 1 ? external signal input to programmable gain amplifiers aux_in2 auxiliary input 2 ? external signal input to programmable gain amplifiers aaf0 external capacitor filter node for programmable gain amplifier 0 (anti ? aliasing) aaf1 external capacitor filter node for programmable gain amplifier 1 (anti ? aliasing) msw0_a multi ? switch 0 a terminal msw0_b multi ? switch 0 b terminal msw0_c multi ? switch 0 common terminal msw1_a multi ? switch 1a terminal msw1_b multi ? switch 1 b terminal msw1_c multi ? switch 1 common terminal msw2_a multi ? switch 2 a terminal msw2_b multi ? switch 2 b terminal msw2_c multi ? switch 2 common terminal msw3_a multi ? switch 3 a terminal msw3_b multi ? switch 3 b terminal msw3_c multi ? switch 3 common terminal vdbl output voltage from on ? chip charge pump; filtering capacitor required vbata main power supply input (analog) vbat main power supply input (digital and related support blocks) vcp output voltage from charge pump regulator; filtering capacitor required vddd output voltage from digital supply regulator; filtering capacitor required ilv programmable current sink for led backlight drive and intensity trimming vddio0 power supply input for digital i/o pins, excluding if4 vddio1 power supply input for if4 mixed ? signal lcd i/o pins vref output voltage from on ? chip precision voltage reference; filtering capacitor required
Q32M210 http://onsemi.com 17 table 2. detailed pin descriptions pin name description iref output current from on ? chip current reference; reference resistor (300 k , low ? tc) required vadc output voltage from adc power supply regulator; filtering capacitor required vlcd0 output voltage from lcd driver (33%); filtering capacitor required vlcd1 output voltage from lcd driver (66%); filtering capacitor required vlcd power supply input for lcd and backlight current driver cp0 charge pump flyback capacitor connection cp1 charge pump flyback capacitor connection vss ground pin in the center of the package usbxtal0 48 mhz usb crystal connection usbxtal1 48 mhz usb crystal connection rtcxtal0 32.768 khz real ? time ? clock crystal connection rtcxtal1 32.768 khz real ? time ? clock crystal connection extclk external clock i/o alt0 sensor interface 3:1 mux common terminal (connection to a0_in0, a0_in1, a0_in2) alt1 sensor interface 5:1 mux common terminal (connection to a0_in3, a0_in4, a0_in5, a0_in6, a0_in7) a0_in0 sensor interface 8:1 mux 0 terminal a0_in1 sensor interface 8:1 mux 1 terminal a0_in2 sensor interface 8:1 mux 2 terminal a0_in3 sensor interface 8:1 mux 3 terminal a0_in4 sensor interface 8:1 mux 4 terminal a0_in5 sensor interface 8:1 mux 5 terminal a0_in6 sensor interface 8:1 mux 6 terminal a0_in7 sensor interface 8:1 mux 7 terminal a0_in opamp a0 negative input terminal (common terminal for sensor interface 8:1 mux) a1_in opamp a1 negative input terminal a2_in opamp a2 negative input terminal a0_ref opamp a0 positive input terminal a1_ref opamp a1 positive input terminal a2_ref opamp a2 positive input terminal a0_outa opamp a0 output (primary) a0_outb opamp a0 output (secondary) a1_outa opamp a1 output (primary) a1_outb opamp a1 output (secondary) a2_outa opamp a2 output (primary) a2_outb opamp a2 output (secondary) spst0_a single ? pole single ? throw switch 0 a terminal spst0_b single ? pole single ? throw switch 0 b terminal spst1_a single ? pole single ? throw switch 1 a terminal spst1_b single ? pole single ? throw switch 1 b terminal spst2_a single ? pole single ? throw switch 2 a terminal spst2_b single ? pole single ? throw switch 2 b terminal spst3_a single ? pole single ? throw switch 3 a terminal spst3_b single ? pole single ? throw switch 3 b terminal test test input; short to vss required
Q32M210 http://onsemi.com 18 pin connections the following table describes the required and recommended external connections and components. these connections and components are required to ensure proper device operation and performance. table 3. required and recommended external connections and components pin external connection or component recommended value vddd power supply filtering capacitor c = 22 f vcpldo power supply filtering capacitor c = 22 f aaf0 anti ? aliasing filtering capacitor c = 1 f (for 160 ? 320 hz cut ? off range) aaf1 anti ? aliasing filtering capacitor c = 1 f (for 160 ? 320 hz cut ? off range) vdbl power supply filtering capacitor c = 10 f vbata battery supply filtering capacitor c = 22 f vbat battery supply filtering capacitor c = 22 f cp0, cp1 charge pump capacitor between cp0, cp1 c = 1 f vddio0 i/o supply filtering capacitor c = 22 f vddio1 i/o supply filtering capacitor c = 22 f vddusb battery supply filtering capacitor c = 10 f rtcxtal0, rtcxtal1 crystal for real ? time clock (no capacitors required) f = 32768 hz, c = 9 pf, esr = 70 k usbxtal0, usbxtal1 crystal for usb (no capacitors required) f = 48.0 mhz, c = 10 pf, esr = 70 vref power supply filtering capacitor c = 22 f iref current reference resistor r = 300 k ( 1%, |tc| < 100 ppm/c) vadc power supply filtering capacitor c = 22 f vlcd power supply filtering capacitor c = 1 f vlcd1 lcd driver voltage filtering capacitor c = 1 nf vlcd0 lcd driver voltage filtering capacitor c = 1 nf nmi test point recommended test test pin must be connected to vss thermal thermal must be connected to battery vss usbdp, usbdn esd protection for usb bus p/n = on semiconductor nup2201mr6t1g table 4. absolute maximum ratings parameter symbol min max units input voltage on any digital pin ? 0.3 3.6 v input voltage on any analog pin ? 0.3 3.6 v input voltage on any supply pin ? 0.3 3.6 v current on any digital pin 5 ma current on any analog pin 10 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
Q32M210 http://onsemi.com 19 table 5. recommended operating conditions parameter symbol min typ max units power supply applied to vbat vbat 1.8 3.3 3.5 v power supply applied to vbata vbata 2.2 3.3 3.5 v internal oscillator clock frequency 1 16 mhz externally supplied clock frequency 16 mhz ambient operating temperature range ta 0 50 c junction temperature range tj 0 75 c opamp differential mode voltage 5 mv table 6. esd and latch ? up characteristics parameter conditions max units esd ? human body model (note 8) jedec js ? 001 ? 2010 vbat pin 1250 v spst[0:3], msw[0:2] pins 1500 all other pins 3000 esd ? charged device model (note 8) jesd22 ? c101 ? e, all pins 750 v esd ? machine model (note 8) jese22 ? a115 ? c, all pins 250 v latch ? up (note 8) jedec std ? 78, all pins 100 ma 8. characteristics are obtained through device qualification and characterization and not tested in production
Q32M210 http://onsemi.com 20 electrical characteristics test conditions typical values unless otherwise noted, typ values specify the typical values based on design and characterization data under normal operating conditions. normal operating conditions include a supply voltage (vbat and vbata) of 3.3 v and an operating temperature of 25 c. for specific blocks the details of the normal operation conditions are described in their respective sections. minimum and maximum values unless otherwise noted, for range parameters, min and max values specify the designed range or measurement range and are guaranteed by design and/or characterization. range parameters include the term ?range? in their name. for non ? range parameters, the min and max values specified may be based on factory production test limits, design, or characterization data. production test limits are specified for typical temperature and supply voltage only. temperature range a ? in the conditions field for any parameter denotes characterized over the complete operating temperature range. the typ values listed for those parameters are guaranteed by design and/or characterization over the complete range. if present, the min and max values for ? parameters may be based on factory production test limits, design, or characterization data. for more information related to the performance of the device across the operating temperature range refer to the typical operating conditions plots. normal operating conditions unless otherwise noted, normal operating conditions indicate an ambient temperature ta = 25 c and a supply voltage vbat = vbata = 3.3 v. vddd, vadc, vref, and the internal oscillator are calibrated to their preset factory calibration settings and correspond to their respective typ values. vddio0 and vddio1 are powered externally from the vddd digital supply regulator. no external loads are applied to digital i/o or analog pins. the power supply for normal operating conditions is shown in figure 3. figure 3. normal operating condition configuration vref precision reference vddd regulator + ? vbata 3.3 v vss vadc regulator sensor interface, if5 vadc vref vddd ibat iref vddio0 vddio1 4 4 rtcxtal1 rtcxtal0 usbxtal1 usbxtal0 vddusb vbat rtc_xtal usb_xtal rtc + ? 3.3 v c vddd c vref c vadc c vbat r iref
Q32M210 http://onsemi.com 21 table 7. normal operation configuration symbol description value c vref vref filtering capacitor 22 f c vddd vddd regulator filtering capacitor 22 f c vadc vadc regulator filtering capacitor 10 f c vbat supply filtering capacitor 22 f usb_xtal crystal for usb 48 mhz rtc_xtal crystal for rtc 32.768 khz r iref resistor for current reference 300 k table 8. system (typical operating conditions (ta = 25 c, vbat = vbata = 3.3 v, vddio0 = vddio1 = vddd, 16 ? bit/32 ? bit mixed instructions, 66% execution from flash memory, data access from sram, sensor interface disabled, peripherals disabled) unless otherwise noted. ? denotes characterized over complete temperature range. current consumption for individual blocks may be found in their respective sections.) parameter symbol conditions min typ max units dc electrical characteristics main supply voltage range (note 9) vbat 1.8 3.6 v analog supply voltage range (note 10) vbata 2.2 3.6 v usb supply voltage range vddusb 3.0 3.3 v i/o supply voltage range (notes 11, 12) vddio0 , vddio1 1.8 3.6 v lcd supply voltage range (note 13) vlcd 1.8 3.6 v run mode current (note 14) ibat typical application, execution from flash, analog dis- abled 1 mhz 0.8 ma 2 mhz 1.2 4 mhz 2.1 8 mhz 3.8 16 mhz 7.0 typical application, execution from sram 1 mhz 0.7 2 mhz 1.0 4 mhz 1.7 8 mhz 3.0 16 mhz 5.6 standby mode current rtc enabled 26 a sleep mode current rtc enabled 0.75 a rtc disabled 0.15 9. vbat powers the vddd regulator (for the digital core, peripherals, internal oscillator), vcp regulator (for the charge ? pump) 10. vbata powers the vadc regulator, vref, sensor interface, analog pins, and if5 pins (wakeup) 11. vddio0 powers i 2 c (scl, sda), if0, if1, if2, if3, nmi, rstb, extclk, jtag 12. vddio1 powers if4 13. vlcd powers vlcd0, vlcd1, ilv 14. the current consumption in run mode depends on the complexity of the application (i.e. the number of memory accesses, type o f instruction (16 ? bit or 32 ? bit), program and data storage in flash or sram).
Q32M210 http://onsemi.com 22 table 9. digital i/o pins (if0, if1, if2, if3, jtag, extclk, rstb, nmi, scl, sda) (typical operating conditions (ta = 25 c, vddio0 = vddd, pull ? up/pull ? down enabled) unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc electrical characteristics vddio0 supply voltage range (note 15) vddio0 1.8 3.6 v output low level v ol i ol = 4 ma 0.2 x vddio0 v output high level v oh i ol = ? 4 ma 0.8 x vddio0 v input low level v il 0.2 x vddio0 v input high level v ih 0.8 x vddio0 v pull ? up resistance r pu non ? i 2 c vddio0 = 1.8 v 102 k vddio0 = 3.3 v 34 48 74 i 2 c vddio0 = 1.8 v 1 vddio0 = 3.3 v 1 pull ? down resistance r pd vddio0 = 1.8 v 102 k vddio0 = 3.3 v 34 55 75 pin capacitance c p 5 pf maximum output current i ol , i oh 4 ma input leakage current i l 1 a 15. supply voltage may be lower during standby mode if vddio0 is connected to vddd table 10. lcd i/o pins (if4) (typical operating conditions (t a = 25 c, vddio1 = vbat, gpio mode, pull ? up / pull ? down enabled) unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc electrical characteristics vddio1 supply voltage range (note 16) vddio1 gpio mode 1.8 3.6 v lcd mode vlcd 3.6 output low level v ol i ol = 4 ma 0.2 x vddio1 v output high level v oh i ol = ? 4 ma 0.8 x vddio1 v input low level v il 0.2 x vddio1 v input high level v ih 0.8 x vddio1 v pull ? down resistance r pd vddio1 = 1.8 v 138 k vddio1 = 3.3 v 34 54 75 pin capacitance c p 5 pf maximum current 4 ma 16. supply voltage may be lower during standby mode if vddio1 is connected to vddd
Q32M210 http://onsemi.com 23 table 11. wakeup i/o pins (if5) (typical operating conditions (ta = 25 c, pull ? up / pull ? down enabled, gpio mode) unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc electrical characteristics if5 supply voltage range (note 17) vbata 1.8 3.6 v output low level v ol i ol = 4 ma 0.2 x vbata v output high level v oh i ol = ? 4 ma 0.7 x vbata v input low level v il 0.2 x vbata v input high level v ih 0.7 x vbata v wakeup threshold (note 18) for if5.0, if5.1 0.2 x vbata v for if5.2, if5.3 0.2 x vbata pull ? up resistance r pu vbata = 1.8 v 102 k vbata = 3.3 v 42 pull ? down resistance r pd vbata = 1.8 v 140 k vbata = 3.3 v 34 54 75 pin capacitance c p 5 pf maximum current 4 ma 17. if5 wakeup pins are powered from vbata 18. wakeup condition for if5.0, if5.1 is falling edge. wakeup condition for if5.2, if5.3 is rising edge. specified threshold indicates the maximum and minimum levels for the falling and rising edge final voltages, respectively table 12. usb i/o (usbd+, usbd ? ) (typical operating conditions (ta = 25 c, full ? speed mode, vddusb = 3.3 v) unless otherwise noted. ? denotes over complete temperature.) parameter symbol conditions min typ max units dc & ac electrical characteristics usb supply voltage vddusb 3.0 3.6 v supply current standby 0.5 a operating 450 output low level v ol 0.3 v output high level v oh 2.8 v input low level v il 0.8 v input high level v ih 2.0 v external pull ? up resistance (note 19) 1.425 1.575 k termination voltage for pull ? up 3.0 3.6 v slew rate (note 19) t fr rise time, c l = 50 pf 4 20 ns t ff fall time, c l = 50 pf 4 20 slew rate matching t frff t frff = t fr /t ff 90 111 % pin capacitance c p 20 pf 19. external pull ? up to 3.3 v is required on d+ to enumerate as a usb 2.0 full ? speed device
Q32M210 http://onsemi.com 24 table 13. flash memory (typical operating conditions (ta = 25 c) unless otherwise noted. all parameters in this section are obtained through qualification and characterization and are not tested in production ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc electrical characteristics supply voltage vbat 1.8 3.6 v write endurance on ? chip ecc disabled 20000 cycles data retention 100 years programming time (per word) 20 s erase time single page 20 ms entire array (note 20) 20 20. erase time for the entire array is through the mass erase operation table 14. spi parameter symbol conditions min typ max units spi clock frequency master mode/slave mode 8.0 mhz spi clock rise and fall time 10 ns data input setup time master mode/slave mode 5 ns data input hold time master mode/slave mode 5 ns data output access time slave mode 50 ns data output disable time slave mode 10 ns data output valid time slave mode (after spi_clk edge) 20 ns data output valid time master mode (after spi_clk edge) 5 ns data output hold time slave mode (after spi_clk edge) 25 ns data output hold time master mode (after spi_clk edge) 10 ns table 15. i 2 c parameter symbol conditions min typ max units scl low time 5 s scl high time 5 s sda setup time 250 ns sda and scl rise time 1000 ns sda and scl fall time 300 ns start condition hold time 4 s table 16. pcm parameter symbol conditions min typ max units pcm_clk 16 mhz pcm_si setup time before pcm_clk edge 10 ns pcm_si hold time after pcm_clk edge 10 ns pcm_so data valid time after pcm_clk edge 50 ns
Q32M210 http://onsemi.com 25 table 17. lcd (if4, vlcd1, vlcd0, ilv) (typical operating conditions (ta = 25 c, vbata = 3.3 v, vlcd = vddio1 = 3.5 v), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vddio1 , vlcd 1.8 3.6 v lcd driving voltage lcd driving voltage 0 vss v lcd driving voltage 1 0.33 x vlcd lcd driving voltage 2 0.66 x vlcd lcd driving voltage 3 vlcd lcd driving voltage temperature drift < 6 ppm/ c lcd backlight current i lv disabled 0.0 0.001 ma setting = 1 x i nom 1.1 setting = 2 x i nom 2.2 setting = 3 x i nom 3.3 setting = 4 x i nom 4.4 setting = 5 x i nom 5.4 setting = 6 x i nom 6.4 setting = 7 x i nom 7.4 setting = 8 x i nom 8.4 setting = 9 x i nom 9.4 setting = 10 x i nom 10.3 table 18. dacs (dac0, dac1, dac2) (typical operating conditions (ta = 25 c, vbata = 3.3 v, dac0 mode 1, code range = 200 to 1023), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbata 2.2 3.6 v supply current code = 200 150 a code = 1023 105 reference voltage dac0 mode 0 vref v dac0 mode 1, dac1, dac2 2 x vref dac0 mode 2 3 x vref resolution 10 bits output dynamic range 58 db output voltage range (note 21) dac0 mode 0 0.15 0.9 v dac0 mode 1 0.15 1.8 dac0 mode 2 0.15 2.7 dac1 0.15 1.8 dac2 0.15 1.8 21. vbata must be greater than the configured output voltage 22. guaranteed monotonic from code 200 to 1023
Q32M210 http://onsemi.com 26 table 18. dacs (dac0, dac1, dac2) (typical operating conditions (ta = 25 c, vbata = 3.3 v, dac0 mode 1, code range = 200 to 1023), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter units max typ min conditions symbol dc & ac electrical characteristics output voltage noise code = 512, bw = 0.1 to 15 hz 25 v rms code = 1023, bw = 0.1 to 15 hz 35 offset error uncalibrated 22 lsb offset error temperature drift 0.08 lsb/ c gain error uncalibrated 35 lsb gain error temperature drift 120 ppm/ c power supply rejection ratio psrr dc 77 db 1 khz 52 output impedance dac0, dac1 35 k dac2 0.11 integral non ? linearity inl code > 200 0.25 lsb differential non ? linearity (note 22) dnl code > 200 guaranteed monotonic 0.25 lsb maximum sink current dac0, dac1 10 a dac2 10 maximum source current dac0, dac1 8 a dac2 130 21. vbata must be greater than the configured output voltage 22. guaranteed monotonic from code 200 to 1023 table 19. internal oscillator (typical operating conditions (ta = 25 c, vbat = 3.3 v, frequency = 3.0 mhz), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbat 1.8 3.6 v frequency range (note 23) f calibrated 1.0 3.0 16.0 mhz frequency step size (note 24) calibrated 1.0 mhz frequency accuracy calibrated 2 % frequency temperature drift ? 60 ppm/ c jitter (note 25) 50 ps power supply rejection ratio psrr dc 50 db 23. internal oscillator is calibrated during production test to all integer frequencies in the frequency range 24. finer frequency steps are possible. for more information, contact on semiconductor 25. peak ? to ? peak jitter
Q32M210 http://onsemi.com 27 table 20. real ? time clock (typical operating conditions (ta = 25 c, vbat = 3.3 v), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbat 1.8 3.6 v supply current 0.60 a frequency (note 26) f 32768 hz duty cycle 50 % 26. exact frequency is dependent on selected crystal and pcb table 21. usb clock (typical operating conditions (ta = 25 c, vbat = 3.3 v), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbat 1.8 3.6 v frequency (note 27) f 48 mhz duty cycle 50 % 27. exact frequency is dependent on selected crystal and pcb table 22. switches (spst0, spst1, spst2, spst3, alt0, alt1, msw0, msw1, msw2, msw3, in0, in1, in2, in3, in4, in5, in6, in7, a0_out[a,b], a1_out[a,b], a2_out[a,b]) (measured at ta = 25 c. all other conditions are typical (vbata = vbat = 3.3 v), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbata 2.2 3.6 v on ? resistance r on 8 10 input voltage range v in vss vbata v open switch leakage spst0, spst1, spst2, spst3, msw0, msw1, msw2 < 100 pa a0_out[a,b], a1_out[a,b], a2_out[a,b] < 100 input mux (in0:in7) source applied to inx, leakage measured at a0_in < 100 alt0 source applied to a0_in0, leakage measured on alt0 < 100 alt1 source applied to a0_in3, leakage measured on alt1 < 100 continuous current (per switch) 10 ma
Q32M210 http://onsemi.com 28 table 23. power supervisor (typical operating conditions (ta = 25 c), unless otherwise noted. ? denotes characterized over complete temperature range. power supervisor is only enabled during initial battery insertion and run mode. the power superviso r is disabled during sleep mode and standby mode.) parameter symbol conditions min typ max units dc & ac electrical characteristics vbat reset threshold falling 1.5 v vddd reset threshold vddd th0 rising 1.75 v vddd th1 falling 1.65 wakeup time (note 28) from battery insertion 0.5 ms from sleep mode 0.5 from standby mode 0.5 enter sleep mode time from run mode 1 ms enter standby mode time from run mode 1 ms 28. wakeup time is measured starting from the moment the vddd voltage exceeds the vddd reset threshold (rising) until the execut ion of the first user instruction in flash. the actual wakeup time will be affected by the number of entries in the nvic table for the app lication. table 24. vddd digital supply regulator (typical operating conditions (ta = 25 c, vbat = 3.3 v), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbat 1.8 3.6 v output voltage vddd run mode ? 1.8 1.85 1.9 v standby mode, iload = 1 ma 1.10 v load regulation resistive load ? 1 mv/ma power supply rejection ratio psrr dc 50 db 1 khz 45 table 25. vadc analog supply regulator (typical operating conditions (ta = 25 c, vbata = 3.3 v, no load), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbata 2.2 3.6 v supply current (note 29) enabled 2 a output voltage v adc ? 1.80 1.85 1.9 v load regulation resistive load ? 2 mv/ma power supply rejection ratio psrr dc 70 db 1 khz 65 start ? up time within 0.1% of final value 500 sec 29. total current of enabled vref and vadc
Q32M210 http://onsemi.com 29 table 26. vcp charge pump supply regulator (typical operating conditions (ta = 25 c, vbat = 3.3 v, no load), unless otherwise noted. ? denotes characterized over complete temperature range) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbat 1.8 3.6 v output voltage vcp 1.74 1.80 1.92 v load regulation resistive load, 125 khz, i load = 0 to 25 ma ? 2 mv/ma power supply rejection ratio psrr dc 60 db 1 khz 60 start ? up time within 0.1% of final value 500 sec table 27. vdbl charge pump (typical operating conditions (ta = 25 c, vbata = 3.3 v, no load, cp_clk = 125 khz), unless otherwise noted. ? denotes characterized over complete temperature range) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbat 1.8 3.6 v supply current enabled 200 a output voltage vdbl 3.4 3.5 3.6 v load regulation (note 30) resistive load ? 4 mv/ma output ripple i load = 10 ma, 125 khz 23 mv pk ? pk output noise bw = 0.1 to 15 hz 75 v rms power supply rejection ratio psrr dc 55 db 1 khz 40 start ? up time within 0.1% of final value 1000 sec 30. load regulation is non ? linear across loads. stated va lue is extrapolated from best ? fit linear curve to measured data. see typical characteristics plot for more information.
Q32M210 http://onsemi.com 30 table 28. vref precision voltage reference (typical operating conditions (ta = 25 c, vbata = 3.3 v, no load), unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc & ac electrical characteristics supply voltage vbata 2.2 3.6 v supply current (note 31) enabled 2 a output voltage vref ta = 25 c 0.898 0.900 0.902 v output voltage temperature drift ta = 15 to 35 c < 50 ppm/ c ta = 5 to 45 c < 50 ta = 0 to 50 c ? 50 load regulation (note 32) resistive load ? 2 mv/ma output noise bw = 0.1 to 15 hz 35 v rms power supply rejection ratio psrr dc 85 db 1 khz 75 start ? up time within 0.1% of final value 700 sec 31. total current of enabled vref and vadc 32. tested to a maximum current load of 2 ma table 29. opamps (a0, a1, a2) (typical operating conditions (ta = 25 c, vbata = 3.3 v, unity gain, v cm = vbata/2) unless otherwise noted. ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc electrical characteristics supply voltage vbata 2.2 3.6 v supply current (per opamp) enabled 12 a input offset voltage v io v cm < vbata ? 0.85 v 1 mv v cm < vbata ? 0.70 v 2 input offset temperature drift v cm = vbata ? 0.8 v ? 2 v/ c input bias current i b < 100 pa input offset current i io < 100 pa input common mode voltage range for cmrr > 75 db 0 vbata ? 0.7 v common mode rejection ratio cmrr 0.1 v < v cm < vbata ? 0.85 v 100 db 0 v < v cm < vbata ? 0.7 v < 100 power supply rejection ratio psrr dc 87 db 1 khz 70 output sink current 10 a output short circuit current i o 1 ma ac electrical characteristics output noise bw = 0.1 to 15 hz 1.5 v rms slew rate sr rising, cl = 30 pf, vac = 350 mv rms 90 mv/ s falling, cl = 30 pf, vac = 350 mv rms 70 gain bandwidth product gbw cl = 50 pf, vac = 200 mv rms 30 khz phase margin 60 deg
Q32M210 http://onsemi.com 31 table 30. adcs (pga0 and adc0, pga1 and adc1) (typical operating conditions unless otherwise noted (ta = 25 c, vbata = 3.3 v, unity gain, vref= 0.9 v, v cm = vbata/2, a = 0.9 v, b = vss, gain = 0 db, mclk = 1.5 mhz, data rate = 1 ksps). ? denotes characterized over complete temperature range. pga0 only supports pga mode (0,0). noise measurement bandwidth is 0.1 hz to 15 hz. cut ? off = 160 hz (aaf cap = 1 f).) parameter symbol conditions min typ max units dc electrical characteristics supply voltage vbata 2.2 3.6 v supply current (per channel) pga and adc enabled 165 a adc resolution 16 bits data rate for specified performance 1000 sps input voltage range (notes 33, 34) v a , v b mode 0 0 vbata ? 1.0 v mode 1 1.00 vbata ? 0.05 mode 2 0 vbata ? 0.05 output voltage range (note 35) 0 vadc v output code range (note 36) mode = unsigned integer 0000 7fff ffff lsb (hex) mode = 2?s complement 8000 0000 7fff reference voltage vref v gain range ? 0 36 db gain step size 6 db gain error (note 37) uncalibrated 524 lsb calibrated < 1 gain error temperature drift tbd lsb/ c offset error (note 38) a = b = vss 1800 lsb calibrated < 1 offset error temperature drift a = b = vss tbd lsb/ c aliasing filter cut ? off frequency range a = v ac 160 320 hz integral nonlinearity (note 39) inl 0.1 v < a < vadc ? 0.1 v, b = vss tbd lsb differential nonlinearity dnl 0.1 v < a < vadc ? 0.1 v, b = vss 1 lsb common mode rejection ratio cmrr vss < a, b < vbata ? 1.0 v, a = b tbd db power supply rejection ratio psrr dc 60 db 1 khz 60 input current inputs a & b < 100 pa dynamic range (note 40) data rate = 10 sps tbd db data rate = 125 sps tbd data rate = 1000 sps tbd decimation filter settling time decimation ratio = 1 6.2 ms decimation ratio = 10 62 decimation ratio = 100 620 line frequency rejection decimation ratio > 12 110 db 33. applies to pga inputs a and b; modes for inputs a and b may be configured independently 34. pga0 can only be configured as mode (0, 0) 35. output voltage is the voltage seen by the adc 36. typical represents code for an input of vref 37. gain error is the cumulative gain error of the pga and adc 38. offset error is the cumulative offset error of the pga and adc 39. calculated using best ? fit curve method 40. data rate adjustments for dynamic range improvement are done through the decimation filter setting 41. cut ? off frequency is the ? 3 db attenuation for small signals. assumes aaf cap = 1 f
Q32M210 http://onsemi.com 32 table 31. pga0 voltage comparator (typical operating conditions unless otherwise noted (ta = 25 c, vbata = 3.3 v). ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc electrical characteristics supply voltage vbata 2.2 3.6 v detection thresholds setting = 40 mv 40 mv setting = 80 mv 80 setting = 120 mv 120 detection time (note 42) < 3 s 42. time from voltage level exceeding threshold to assertion of interrupt table 32. temperature sensor (typical operating conditions unless otherwise noted (vbata = 3.3 v). ? denotes characterized over complete temperature range.) parameter symbol conditions min typ max units dc electrical characteristics supply voltage vbata 2.2 3.6 v temperature sense range 0 50 c temperature sense accuracy (note 43) 0 < ta < 50 1.5 c 10 < ta < 40 1.0 15 < ta < 35 0.8 43. accuracy after factory calibration
Q32M210 http://onsemi.com 33 typical operating characteristics (opamps) (t a = 25 c and vbata = 3.3 v, unless otherwise noted) t = 0 c figure 4. input offset vs. common ? mode voltage figure 5. rising slewrate vs. supply voltage common ? mode input voltage (v) vbata voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.3 0.5 0.8 1.0 1.3 1.5 3.6 3.2 2.8 2.4 2.0 0.05 0.06 0.07 0.08 0.09 0.10 figure 6. falling slewrate vs. supply voltage figure 7. rising slewrate vs. input level vbata voltage (v) ac input level (vrms) 3.6 3.2 2.8 2.4 2.0 0 0.01 0.02 0.03 0.04 0.05 0.45 0.43 0.41 0.39 0.37 0.35 0.06 0.07 0.08 0.09 0.10 0.11 0.12 figure 8. falling slewrate vs. input level figure 9. time vs. voltage output for input step ac input level (vrms) time ( s) 0.45 0.43 0.41 0.39 0.37 0.35 0 0.01 0.02 0.03 0.04 0.05 20 16 12 8 4 ? 4 ? 8 ? 12 0.8 1.0 1.2 1.6 1.8 2.0 2.4 2.6 input offset voltage (mv) rising slew ? rate (v/ s) falling slew ? rate (v/ s) rising slew ? rate (v/ s) falling slew ? rate (v/ s) voltage (v) t = 25 c t = 50 c t = 0 c t = 25 c t = 50 c t = 0 c t = 25 c t = 50 c vbata ? 0.8 vss+0.001 vbata ? 0.7 t = 0 c t = 25 c t = 50 c 024 1.4 2.2 t = 0 c t = 25 c t = 50 c vac = 0.45 vrms vac = 0.35 vrms input output input output
Q32M210 http://onsemi.com 34 typical operating characteristics (vref precision reference) (t a = 25 c and vbata = 3.3 v, unless otherwise noted) figure 10. vref vs. temperature figure 11. vref vs. load temperature ( c) load current (ma) 50 40 30 20 10 0 ? 300 ? 250 ? 200 ? 150 ? 100 ? 50 0 2.0 1.75 1.5 1.25 1.0 0.75 0.5 897.0 897.5 898.0 898.5 899.0 899.5 900.0 figure 12. vref vs. supply voltage vbata voltage (v) 3.6 3.2 2.8 2.4 2.0 899.5 899.6 899.7 899.8 899.9 900.0 voltage drift from maximum ( v) vref voltage (mv) vref voltage (mv) t = 25 c t = 50 c t = 0 c t = 25 c t = 50 c t = 0 c
Q32M210 http://onsemi.com 35 typical operating characteristics (adcs) (t a = 25 c and vbata = 3.3 v, unless otherwise noted) figure 13. gain vs. temperature (0 db) temperature ( c) 50 40 30 20 10 0 ? 0.050 ? 0.045 ? 0.040 ? 0.035 ? 0.030 ? 0.025 ? 0.020 figure 14. gain vs. temperature (12 db) figure 15. gain vs. temperature (30 db) temperature ( c) temperature ( c) 50 40 30 20 10 0 11.935 11.940 11.945 11.950 11.955 11.960 11.965 50 40 30 20 10 0 29.96 29.97 29.98 30.00 30.01 30.03 30.04 30.05 gain (db) gain (db) gain (db) 0 db gain setting 12 db gain setting 29.99 30.02 30 db gain setting
Q32M210 http://onsemi.com 36 typical operating characteristics (dacs) (t a = 25 c and vbata = 3.3 v, unless otherwise noted) figure 16. dac inl vs. input code figure 17. dac dnl vs. input code input code input code 1000 800 600 400 200 ? 0.5 ? 0.4 ? 0.3 ? 0.2 ? 0.1 0.2 0.3 0.5 1000 800 600 400 200 ? 0.20 ? 0.15 ? 0.10 ? 0.05 0.05 0.10 0.15 0.20 inl (lsb) dnl (lsb) 0 0.1 0.4 t = 25 c 0 t = 25 c figure 18. dac low code behavior input code 500 400 200 100 0 0 0.1 0.2 0.3 0.6 0.7 0.8 0.9 output voltage (v) 0.4 t = 25 c 300 0.5 typical operating characteristics (temperature sensor) (t a = 25 c and vbata = 3.3 v, unless otherwise noted) figure 19. temperature sensor vs. temperature temperature ( c) 50 40 30 20 10 0 15500 16000 16500 17000 17500 18000 18500 adc output code (lsb) error single ? point calibration ideal measured ? 3 ? 2 ? 1 0 1 2 3 temperature error ( c)
Q32M210 http://onsemi.com 37 typical operating characteristics (switches) (t a = 25 c and vbata = 3.3 v, unless otherwise noted) figure 20. on resistance vs. input voltage input voltage (v) 3.6 3.0 1.8 1.2 0.6 0 0 4 8 12 16 20 on resistance ( ) vbata = 2v2 2.4 vbata = 3v3 vbata = 3v6 typical operating characteristics (vdbl charge pump) (t a = 25 c and vbata = 3.3 v, unless otherwise noted) figure 21. vdbl vs. time figure 22. vdbl vs. frequency time (s) frequency (hz) 30 24 18 12 6 0 ? 300 ? 200 ? 100 0 100 200 300 15 12 9 6 3 0 ? 160 ? 150 ? 130 ? 120 ? 100 ? 80 ? 70 ? 60 vdbl difference from mean ( v) vdbl noise power (dbv) ? 90 ? 11 0 ? 140
Q32M210 http://onsemi.com 38 detailed function descriptions powering figure 23. typical powering configuration + ? vbata +3.3 v from battery sensor interface, if5 vddio0 vddio1 vddusb +5 v from usb vbat regulator 3.3 v vdbl charge pump vdbl digital subsystem including cortex ? m3 processor vcp regulator vddd regulator rtc vddd optional (required for usb) ilv optional (backlight) arm 3.3 v in the typical powering configuration the regulators, rtc, and the sensor interface (including vadc and vref) are powered directly by the battery. the operating voltage ranges and related parameters of sensor interface components including the opamps, pgas, dacs, and switches are limited by the actual voltage level of the battery. as the battery voltage changes over its life time the operating ranges will change accordingly. figure 24. extended powering configuration + ? vbata +3.3 v from battery sensor interface, if5 vddio0 vddio1 vddusb +5 v from usb vbat 3.3 v regulator vdbl charge pump vdbl digital subsystem including arm processor vcp regulator vddd regulator rtc vddd optional (required for usb) ilv optional (backlight) vbata provided by charge pump cortex ? m3 3.3 v in the extended powering configuration the regulators and rtc are powered directly by the battery. the sensor interface (including vadc and vref) is supplied by the on ? chip charge pump. this is implemented by connecting the vdbl pin to the vbata pins externally. since the vcp regulator and charge pump are powered from vbat, the operating voltage for the sensor interface will be the vdbl voltage. the operating voltage ranges and related parameters of the sensor interface components including the opamps, pgas, dacs, and switches are limited by the fixed voltage level of the vdbl. as the battery voltage changes over its life time the operating ranges will remain fixed as long as the battery voltage is sufficient to operate the charge pump. the external wakeup pins (if5) are powered from vbata. to ensure proper powering of the wakeup pins when in sleep mode and standby mode, an external diode must be connected between the battery and vbata pins. this results in a suitable supply voltage on vbata when the charge pump is disabled.
Q32M210 http://onsemi.com 39 usb oscillator external crystal usb_clk rtc oscillator external crystal to rtc and nvic internal rc_osc rtc div rtc_osc usbxtal0 usbxtal1 rclk selection rclk rtcxtal0 rtcxtal1 ext_clk ext_clk div rtc_clk to ext_clk detect figure 25. clocking oscillator
Q32M210 http://onsemi.com 40 figure 26. sensor interface vss a0_ref a0_in a0_out to pga input mux a0_in2 alt0 select alt0 a0 in select (m0) vbata vss a2 a2_ref a2_in a2_out vbata vss a1 a1_ref a1_in a1_out to pga input mux a0 alt1 select alt1 off off off off off off off off vbata to pga input mux ? + ? + ? + off off a0_outb a1_outa off off a2_outb off off a2_outa a1_outb a0_outa a0_in1 a0_in0 a0_in3 a0_in4 a0_in5 a0_in6 a0_in7 the external sensor interface consists of multiplexers, opamps, and switches. the device contains an 8:1 analog mux which allows up to eight sensors to be connected to the negative terminal of opamp a0. the inputs to the mux are a0_in0 through a0_in7. the device contains two alternate multiplexers alt0 and alt1. alt0 is a 3:1 analog mux allowing a0_in0 through a0_in2 to be connected to the alt0 pin. alt1 is a 5:1 analog mux allow a0_in3 through a0_in7 to be connected to the alt1 pin. when signals are connected to alt0 or alt1, they may also optionally be connected to the negative terminal of opamp a0. the muxs feature low ? impedance paths for connected channels and high isolation of unconnected channels. the switches are implemented using specialized transistors ensuring ultra low leakage into the signal path from the power supplies, voltage references, and other system blocks. the three on ? chip opamps a0, a1, and a2 support a nominal common ? mode input range from 0 v to vbata ? 0.7 v. the output swings to a maximum of vbata ? 50 mv. the opamps are designed to have a very high power supply rejection ratio and are thus able to reject variations in the battery supply. this allows for a low noise interface to the sensor which is effectively isolated from any voltage ripple or spikes that may appear on the power supply. the opamps support feedback resistors up to 5 m in a transimpedance (tia) configuration without compromising stability. the device contains four single ? pole single ? throw (spst) switches. when the switch is closed the resulting channel features very low impedance allowing for nearly transparent routing of voltage and current signals. the voltage headroom for the channel is related to the analog supply voltage, vbata. the spsts are designed to avoid trapped charge when the switch state changes from closed to open.
Q32M210 http://onsemi.com 41 dual pgas +adcs figure 27. dual pgas +adcs adc0 + decimator 16:2 mux vss vbat/2 vbata/2 vref a0_out vss mclk 32 pga0 vbata vbata a b vref vadc aaf0 aaf1 aux_in[2:0] vadc/2 3 adc0 data detect_vt detect_output vss vss adc1 + decimator vss 32 vref vadc adc1 data a1_out a2_out vwakeup vts a b a0_ref a1_ref a2_ref 16:2 mux cmp mclk pga1 vss vbat/2 vbata/2 vref a0_out aux_in[2:0] vadc/2 3 a1_out a2_out vwakeup vts a0_ref a1_ref a2_ref the device contains two independent input channels each with a 16 ? bit analog ? to ? digital converter (adc), programmable gain amplifier (pga), and signal multiplexer (mux). the mux selects from a range of internal and external signals used for system operation, or signals connected to the external sensor interface. the inputs to the mux include: ? vss ? ground ? vbat/2 ? battery voltage divided by 2 ? vbata/2 ? battery voltage for sensor interface divided by 2 ? vref ? precision voltage reference ? vadc/2 ? vadc analog supply regulator voltage divided by 2 ? a0_out ? output of opamp a0 ? a1_out ? output of opamp a1 ? a2_out ? output of opamp a2 ? a0_ref ? positive terminal input of opamp a0 ? a1_ref ? positive terminal input of opamp a1 ? a2_ref ? positive terminal input of opamp a2 ? vwakeup ? voltage from if5.0 ? vts ? temperature sensor voltage reading ? aux_in0 ? auxiliary input 0 ? aux_in1 ? auxiliary input 1 ? aux_in2 ? auxiliary input 2 the mux selects two of the inputs for va and vb (the inputs to pga input a and pga input b, respectively). the output of the pga is the dif ferential voltage between va and vb with a selectable gain applied. in many sensor configurations it is desirable to select va as the output of an opamp, and vb as the corresponding positive terminal input of the same opamp. the output of the pga in this configuration is the difference in voltage between the opamp positive terminal input and output which is directly related to the sensor impedance and external feedback resistor value. the vb bias voltage is subtraced off resulting in a net differential voltage of 0 v when the sensor impedance is high. the pga is equipped with an anti ? aliasing filter. an internal resistance coupled with an external capacitor applied to the aaf pin creates a first order low ? pass filter. the ? 3 db cut ? off frequency is programmable to allow for flexible bandwidth of the pga output. the bandwidth may be adjusted by reconfiguring the internal resistance and selecting the appropriate aaf capacitor. the adc has a resolution of 16 ? bits with an input voltage range between 0 v and 1.8 v. the adc operates by oversampling the pga output voltage to reduce noise and to obtain superior linearity. the reference voltage for conversions is the on ? chip vref precision voltage reference at 0.9 v. the selection of the number format is configured by the application. the output number format of the adc can be mapped in two ways:
Q32M210 http://onsemi.com 42 1. 2?s complement ? a 0 v input corresponds to 0x8000, and a maximum input results in 0x7fff. 2. unsigned ? a 0 v input corresponds to 0x0000, and a maximum input results in 0xffff. the nominal adc data rate is 1000 samples/second for a system clock of 3.0 mhz and an mclk divisor of 1. the adc sampling is periodic. samples are provided at the same period regardless of the voltage level. faster data rates are obtained by reconfiguring the adc clock and configuration. lower data rates are obtained through decimation of the base rate. the hardware ? based decimation filters are implemented using cascaded, programmable low ? pass filters of variable length. this architecture enables the application to sample data at any desired rate including rates down to 10 samples/second. the filters are designed to provide more than 100 db rejection of common line frequencies (50/60 hz) at this rate. reducing the adc data rate through the decimation filter provides an increase in the signal ? to ? noise ratio by reducing the number of noise bits. this results in an increase in the signal dynamic range. reconfiguring the adc clock to obtain faster data rates requires careful selection of the pga aaf capacitor to ensure adequate filtering and signal bandwidth. the pga + adc feature low gain and of fset temperature drifts making them ideal for systems where calibration may be performed at a single known temperature but the operating condition may vary. the digital output of the adc is connected to a hardware gain and offset correction unit. the absolute gain and offset of the signal chain may be calibrated using external known voltages or voltages based on vref. the calibration factors are configured in the gain and offset correction unit. all subsequent samples are automatically adjusted by these factors. pga0 includes a voltage detect comparator with programmable thresholds. when the comparator is enabled a signal is provided to the arm cortex ? m3 processor that indicates when the pga0 output voltage exceeds the threshold. the application may use the signal to enable the adc or other system blocks to perform a sensor measurement. this results in lower overall current consumption since the adc may be disabled while waiting for a specific voltage level to occur. triple dacs figure 28. triple dacs dac0 ref select dac0 code dac0 vref 2 x vref 3 x vref dac1 dac2 dac1 code dac2 code 2 x vref dac1 dac2 vbata vss 2 x vref buffer three digital ? to ? analog converters (dacs) are available. each dac is implemented using a current steering network to minimum power consumption. the dacs have 10 ? bits of resolution. the reference voltage is selectable on dac0 and fixed on dac1 and dac2. the effective voltage per lsb is determined by the reference voltage. the dac outputs are buffered to ensure sufficient drive capability of the reference terminal of the on ? chip opamps and auxiliary analog inputs. dac0 provides the highest level of reference voltage flexibility by allowing the dynamic range of the converter to be mapped into three ranges: 1 x vref, 2 x vref, and 3 x vref. the first range, vref, provides maximum voltage resolution per lsb. the second range, 2 x vref, provides a compromise between resolution per lsb and output voltage range. the third range, 3 x vref, provides a lowest resolution per lsb but the largest output range.
Q32M210 http://onsemi.com 43 dac1 and dac2 have a fixed output dynamic range of vss to 2*vref. dac0 and dac1 are buffered using weak, low power output buffers. the maximum current drawn from these buffers is sufficient to drive the on ? chip opamp inputs. loads should not be connected directly to the dac0 and dac1 outputs to avoid undesired voltage sag. dac2 is buffered using a strong drive output buffer. low impedance loads down to 10 k may be connected directly to the dac2 outputs without significant voltage sag. temperature sensor the temperature sensor utilizes the change in diode voltage drops over two internal transistors to create a proportional temperature output. this voltage (vts) is fed to an adc through one of the pgas where it is sampled and a digital code value is provided to the arm cortex ? m3 processor. the temperature sensor is factory calibrated at 25 c using a one ? point calibration. the calibration value is stored in the flash. analog wakeup pin vbata 757 k 1.05 k vwakeup to wakeup if5.0 vbata vss figure 29. analog wakeup pin controller (typ) (typ) the analog wakeup pin (if5.0) is a basic wakeup pin with the added functionality to measure external impedance. this feature is suitable for applications where the wakeup condition may also have encoded information in the form of impedance. after exiting from sleep or standby modes, the system may inject a small current through the impedance via if5.0 and measure the corresponding proportional voltage. the voltage may be measured through the vwakeup0 signal on the pga and sampled through the adc. in run mode, if5.0 may operate as a gpio pin. by assigning an interrupt to if5.0 the application can detect if the wakeup condition was removed during operation. multi ? switches figure 30. multi ? switches msw 0_a msw 0_b msw 0_c off off msw 1_a msw 1_b msw 1_c off off msw 2_a msw 2_b msw 2_c off off msw 3_a msw 3_b msw 3_c off off the device contains four multi ? switches (msws) each msw may be configured into one of four modes: 1. port a connected to port c 2. port b connected to port c 3. port a & port b connected to port c 4. nothing connected to port c when two ports are connected the resulting channel features very low impedance allowing for nearly transparent routing of voltage and current signals. the voltage headroom for the channel is related to the analog supply voltage, vbata. the msws may each be configured to operate in pulse ? width modulation (pwm) mode. in this mode, the low impedance of the channel makes it possible to directly drive transducers (including loud speakers) or other actuators such as motors, without the need for an external driver. the pwm operation is driven by a dedicated clock. the clock frequency and pwm duty cycle is configurable.
Q32M210 http://onsemi.com 44 battery insertion battery removal battery end ? of ? life supply transient vddd time time voltage figure 31. power supervisor reset vddd th0 vddd th1 operating modes vbat por (internal) vddd internal oscillator rtc run mode battery insertion sleep mode internal oscillator disabled run mode vddd vddd enabled internal oscillator enabled rtc oscillator internal enabled por gets released vddd reaches operating voltage vddd disabled wakeup vddd reaches operating voltage figure 32. entering sleep mode event oscillator enabled starts wakeup0 event 1
Q32M210 http://onsemi.com 45 figure 33. entering standby mode vbat por (internal) vddd internal oscillator rtc run mode battery insertion standby mode internal oscillator disabled run mode vddd vddd restored internal oscillator enabled rtc oscillator internal enabled por gets vddd reaches operating voltage vddd lowered to ~ 1.0 v wakeup vddd reaches operating voltage event oscillator starts released enabled wakeup0 event 1
Q32M210 http://onsemi.com 46 example application diagrams figure 34. glucose meter application rtc 16 ? bit adc0 dac0 strip detection (strip impedance measurement) wakeup controller shared gpio and com/seg pins + ? 16:2 mux vss vddd/2 vbata/2 vref a0_out a1_out a2_out a0_ref a1_ref a2_ref vwakeup vts aux_in2 aux_in0 aux_in1 vadc/2 vss vss vbata vadc vddd vref vss test strip vwakeup vts vss control register file vss arm processor system wakeup0 rtcxtal0 wakeup1 aux_in2 vref rstb rtcxtal1 usbxtal0 usbxtal1 cp0 cp1 vss vdbl vlcd vlcd1 vlcd0 lcd display (up to 112 segments) com[0:3] seg[0:27] vddio0 aaf0 vss vdbl vss rtc_xtal usb_xtal vss internal oscillator iref vdbl 3.3 v vss vcp vss vref reference voltage vadc regulated voltage vlcd1 lcd driver voltages vddd digital and i/o regulated voltage vdbl charge pump voltage brown ? out protection circuitry usb oscillator real ? time oscillator ilv scl eeprom e2 vddd vss temperature sensor vss + a1 vss vbata vss 8:1 m u x a0 work vbata vss a0_in0 a0_in a0_outa a0_out a0_ref dac0 reference counter a1_in a1_outa a1_out pga0 vss vddd esd0 esd1 esd2 esd4 esd3 sda 256 kb flash 48 kb sram vddio1 test vss vbat vss vss vss vss vss vss vss vss vbata ? + ? vss pu s h button vss esd5 gpio32 a1_ref c aaf0 c backlight r temp r therm pu s h button r fb r iref c vref c vddd c vadc c vdbl c pump c vbat c vcp c lcd0 c lcd1 c lcd cortex m 3 clock i 2 c port vlcd0, a0_in1 r cal a0_in2..in7 vss
Q32M210 http://onsemi.com 47 table 33. symbol description suggested part number(s) recom- mended value unit toler- ance c vref vref filtering capacitor 0805 taiyo yuden jmk21213j226mg ? t 22 f 20% c vddd vddd regulator filtering capacitor 0805 panasonic ecj ? 2fb0j226m 22 f 20% c lcd vlcd filtering capacitor 0603 taiyo yuden lmk107b7105ka ? t 1 f 10% c lcd1 vlcd1 filtering capacitor 0402 panasonic ecj ? 0eb1h102k 1 nf 10% c lcd0 vlcd0 filtering capacitor 0402 panasonic ecj ? 0eb1h102k 1 nf 10% c vadc vadc regulator filtering capacitor 0805 taiyo yuden jmk21213j226mg ? t 22 f 20% c vdbl charge pump output filtering capacitor 0603 taiyo yuden jmk107bj106ma ? t 10 f 20% c pump charge pump capacitor 0603 taiyo yuden lmk107b7105ka ? t 1 f 10% c vcp charge pump regulated output filtering capacitor 0805 taiyo yuden jmk21213j226mg ? t 22 f 20% c vbat vbat supply filtering capacitor 0805 taiyo yuden jmk21213j226mg ? t 22 f 20% r fb feedback resistor for transimpedance amplifier application specific r cal calibration resistor for transimpedance amplifier application specific c aaf0 anti ? aliasing filter capacitor 0603 taiyo yuden lmk107b7105ka ? t 1 f 10% c backlight led backlight capacitor 0603 taiyo yuden lmk107b7105ka ? t 1 f 20% usb_xtal usb crystal (optional ? only required for usb operation) abracon abm10 ? 48.000mhz ? e20 ? t ndk1612aa ? 48.000m 48 mhz 20 ppm rtc_xtal rtc crystal abracon abs07 ? 32.768khz ? 9 ? t 32.768 khz 20 ppm e2 eeprom (optional) cat24c16 16 kbit eeprom cat24c32 32 kbit eeprom cat24c64 64 kbit eeprom cat24c128 128 kbit eeprom cat24c256 256 kbit eeprom r temp fixed value resistor for external temperature sensing panasonic erj ? 3ekf2003v 200 k 1% r therm thermistor for external temperature sensing application specific r iref resistor for current reference vishay dale crcw0402300kfked 300 k 1% esd0 esd protection diode on semiconductor esd9l3.3st5g 15 kv (iec 61000 ? 4 ? 2) esd1 esd protection diode on semiconductor esd9l3.3st5g 15 kv iec 61000 ? 4 ? 2) esd2 esd protection diode on semiconductor esd9l3.3st5g 15 kv (iec 61000 ? 4 ? 2) esd3 esd protection diode on semiconductor esd9l3.3st5g 15 kv (iec 61000 ? 4 ? 2) esd4 esd protection diode on semiconductor esd9l3.3st5g 15 kv (iec 61000 ? 4 ? 2) esd5 esd protection diode on semiconductor esd9l3.3st5g 15 kv (iec 61000 ? 4 ? 2)
Q32M210 http://onsemi.com 48 figure 35. usb application Q32M210 + ? vbata +3.3 v from battery vddio0 vddio1 vddusb +5 v vbat 3.3 v vddd pc usb port usbdp usbdn vss esd0 vss esd1 vss vss usb_ldo esd 1 vss physical usb_xtal usbxtal0 usbxtal1 connector c vbat table 34. usb application configuration symbol description suggest part number recommended value unit toler- ance esd0 usb esd protection on semiconductor nup2201mr6t1 transient voltage suppressor esd1 esd protection diode on semiconductor esd9l3.3st5g 15 kv (iec 61000-4-2) usb_ldo low-dropout regulator on semiconductor ncv8560 - 3.3 v, 150 ma, ldo regulator c vbat vbat supply filtering capacitor 0805 taiyo yuden jmk21213j226mg-t 22 f 20% usb_xtal usb crystal abracon abm10-48.000mhz-e20-t ndk1612aa-48.000m 48 mhz 20 ppm software development support software development support for Q32M210 is provided in the q32 evaluation and development kit (edk). the edk is a full software development system built on an industry-standard development tool environment with customized components, system libraries, documentation, and sample code to support specialized application development. the edk is included with the evaluation and development board (with on ? board jtag) suitable for prototype software development and for evaluating Q32M210 with the supplied sample applications. out of the box, the edk leverages iar embedded workbench ? for arm as the baseline development and debug environment. the edk installer can be used with any licensed version of the tools, or with the ewarm kick start kit software release (included) for evaluation purposes. the edk contains sample source code demonstrating many of the on-board peripherals including i2c master and slave, uart, spi, pcm, eeprom access, flash with crc, analog subsystem, operating modes, and basic usb. also included are usb hid (human interface device) and msc (mass storage class) sample binaries leveraging the c/usb software stack product from partner micrium. edk documentation includes a programmer?s guide, hardware reference which explains the Q32M210 hardware and configuration, firmware reference which details the supporting system firmware includes and libraries, the evaluation and development board manual which provides information for evaluation and prototyping using the accompanying development board, and arm reference manuals.
Q32M210 http://onsemi.com 49 package dimensions ? row, staggered ? pad case 513al ? 01 issue o c 0.15 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters 3. coplanarity applies to the exposed pad as well as the terminals. a d e b c 0.08 a1 a d2 l c 0.15 2x 2x seating c 0.10 c e2 140x e b1 b17 a20 a39 b33 b49 a58 b 140x a 0.10 b c 0.05 c dim min max millimeters a 0.50 0.60 a1 --- 0.05 b 0.25 0.35 d 10.00 bsc d2 5.70 5.90 e 10.00 bsc e2 5.70 5.90 e 0.50 bsc l 0.25 0.35 pin one location plane note 3 top view side view bottom view detail a 140x l a39 b33 140x b e e e/2 dimension: millimeters 10.10 0.50 pitch 40x 0.48 100x 0.35 40x 0.48 0.25 100x 0.35 10.10 5.95 5.95 a1 0.50 pitch *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended a1 a76 b64 a 0.15 b c a 0.15 b c e/2 detail a
Q32M210 http://onsemi.com 50 reflow information table 35. tape & reel information units per reel 3000 carrier tape width 24 mm pocket pitch 16 mm cover tape sumitomo 21 mm device orientation on tape upper left table 36. ordering information part number package shipping configuration Q32M210f08alna 140 tllga 3000 / tape & reel esd handling caution: esd sensitive device. permanent damage may occur on devices subjected to high ? energy electrostatic discharges. proper esd precautions in handling, packaging and testing are recommended to avoid performance degradation or loss of functionality. company or product inquiries for more information about on semiconductor?s products or services visit our web site at http://onsemi.com . on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. Q32M210/d arm is the registered trademark and cortex is the trademark of arm limited in the eu and other countries. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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